Cypress CYV15G0404DXB Rxcksela, Rxckselb, Rxckselc, Rxckseld, Rxratea, Rxrateb, Rxratec, Rxrated

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CYV15G0404DXB

 

 

 

 

 

 

 

 

 

 

Table 9. Device Configuration and Control Latch Descriptions (continued)

 

 

 

Name

Signal Description

 

 

RXCKSELA

Receive Clock Select. The initialization value of the RXCKSELx latch = 1. RXCKSELx selects the receive

 

 

RXCKSELB

clock source used to transfer data to the Output Registers and the clock source for the RXCLK± output. When

 

RXCKSELC

RXCKSELx = 1, the associated Output Registers, are clocked by REFCLKx± at the associated RXCLKx±

 

RXCKSELD

output buffer. When RXCKSELx = 0, the associated Output Registers, are clocked by the Recovered Byte

 

 

clock at the associated RXCLKx± output buffer. These output clocks may operate at the character-rate or half

 

 

the character-rate as selected by RXRATEx.

 

RXRATEA

Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select the

 

 

RXRATEB

rate of the RXCLKx± clock output.

 

RXRATEC

When RXRATEx = 1 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow

 

 

RXRATED

 

the recovered clock operating at half the character rate. Data for the associated receive channels should be

 

 

 

 

 

latched alternately on the rising edge of RXCLKx+ and RXCLKx–.

 

 

When RXRATEx = 0 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow

 

 

the recovered clock operating at the character rate. Data for the associated receive channels should be latched

 

 

on the rising edge of RXCLKx+ or falling edge of RXCLKx–.

 

 

When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full rate clock, the RXCLKx± clock outputs are

 

 

complementary clocks that follow the reference clock operating at half the character rate. Data for the

 

 

associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.

 

 

When RXRATEx = 0 with RXCKSELx = 1 and REFCLKx± is a full rate clock, the RXCLKx± clock outputs are

 

 

complementary clocks that follow the reference clock operating at the character rate. Data for the associated

 

 

receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–.

 

 

When RXCKSELx = 1 and REFCLKx± is a half rate clock, the value of RXRATEx is not interpreted and the

 

 

RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half the

 

 

character rate. Data for the associated receive channels should be latched alternately on the rising edge of

 

 

RXCLKx+ and RXCLKx–.

 

SDASEL1A[1:0]

Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0]

 

 

SDASEL1B[1:0]

latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1± Primary

 

SDASEL1C[1:0]

Differential Serial Data Inputs.

 

SDASEL1D[1:0]

When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.

 

 

When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

 

 

When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

 

 

When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

 

SDASEL2A[1:0]

Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

 

 

SDASEL2B[1:0]

SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2±

 

SDASEL2C[1:0]

Secondary Differential Serial Data Inputs.

 

SDASEL2D[1:0]

When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled

 

 

When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

 

 

When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

 

 

When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

 

ENCBYPA

Transmit Encoder Bypassed. The initialization value of the ENCBYPx latch = 1. ENCBYPx selects if the

 

 

ENCBYPB

Transmit Encoder is enabled or bypassed. When ENCBYPx = 1, the Transmit encoder is enabled. When

 

ENCBYPC

ENCBYPx = 0, the Transmit Encoder is bypassed and raw 10-bit characters are transmitted.

 

ENCBYPD

 

 

 

 

 

TXCKSELA

Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock

 

 

TXCKSELB

source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register,

 

TXCKSELC

TXDx[7:0] and TXCTx[1:0], is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit

 

TXCKSELD

path is bypassed. When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input registers,

 

 

TXDx[7:0] and TXCTx[1:0].

 

Document #: 38-02097 Rev. *B

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Bist Transmit ModesTransmit PLL Clock Multiplier Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversClock/Data Recovery ReclockerDeserializer/Framer Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it
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