Cypress CYV15G0404DXB manual Abcdei fghj Name

Page 38

CYV15G0404DXB

Table 14.

Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

Bits

Current RD

Current RD+

 

Data

Bits

Current RD+

 

Byte

 

 

Byte

Current RD

 

Name

HGF EDCBA

abcdei fghj

abcdei fghj

 

Name

HGF EDCBA

abcdei fghj

abcdei fghj

 

D0.0

000 00000

100111

0100

011000

1011

 

D0.1

001 00000

100111 1001

011000 1001

 

D1.0

000 00001

011101

0100

100010

1011

 

D1.1

001 00001

011101 1001

100010 1001

 

D2.0

000 00010

101101

0100

010010

1011

 

D2.1

001 00010

101101 1001

010010 1001

 

D3.0

000 00011

110001

1011

110001

0100

 

D3.1

001 00011

110001 1001

110001 1001

 

D4.0

000 00100

110101

0100

001010

1011

 

D4.1

001 00100

110101 1001

001010 1001

 

D5.0

000 00101

101001

1011

101001

0100

 

D5.1

001 00101

101001 1001

101001 1001

 

D6.0

000 00110

011001

1011

011001

0100

 

D6.1

001 00110

011001 1001

011001 1001

 

D7.0

000 00111

111000

1011

000111

0100

 

D7.1

001 00111

111000 1001

000111 1001

 

D8.0

000 01000

111001

0100

000110

1011

 

D8.1

001 01000

111001 1001

000110 1001

 

D9.0

000 01001

100101

1011

100101

0100

 

D9.1

001 01001

100101 1001

100101 1001

 

D10.0

000 01010

010101

1011

010101

0100

 

D10.1

001

01010

010101 1001

010101 1001

 

D11.0

000 01011

110100

1011

110100

0100

 

D11.1

001

01011

110100 1001

110100 1001

 

D12.0

000 01100

001101

1011

001101

0100

 

D12.1

001

01100

001101 1001

001101 1001

 

D13.0

000 01101

101100

1011

101100

0100

 

D13.1

001

01101

101100 1001

101100 1001

 

D14.0

000 01110

011100

1011

011100

0100

 

D14.1

001

01110

011100 1001

011100 1001

 

D15.0

000 01111

010111

0100

101000

1011

 

D15.1

001

01111

010111 1001

101000 1001

 

D16.0

000 10000

011011

0100

100100

1011

 

D16.1

001

10000

011011 1001

100100 1001

 

D17.0

000 10001

100011

1011

100011

0100

 

D17.1

001

10001

100011 1001

100011 1001

 

D18.0

000 10010

010011

1011

010011

0100

 

D18.1

001

10010

010011 1001

010011 1001

 

D19.0

000 10011

110010

1011

110010

0100

 

D19.1

001

10011

110010 1001

110010 1001

 

D20.0

000 10100

001011

1011

001011

0100

 

D20.1

001

10100

001011 1001

001011 1001

 

D21.0

000 10101

101010

1011

101010

0100

 

D21.1

001

10101

101010 1001

101010 1001

 

D22.0

000 10110

011010

1011

011010

0100

 

D22.1

001

10110

011010 1001

011010 1001

 

D23.0

000 10111

111010

0100

000101

1011

 

D23.1

001

10111

111010 1001

000101 1001

 

D24.0

000 11000

110011

0100

001100

1011

 

D24.1

001

11000

110011 1001

001100 1001

 

D25.0

000 11001

100110

1011

100110

0100

 

D25.1

001

11001

100110 1001

100110 1001

 

D26.0

000 11010

010110

1011

010110

0100

 

D26.1

001

11010

010110 1001

010110 1001

 

D27.0

000 11011

110110

0100

001001

1011

 

D27.1

001

11011

110110 1001

001001 1001

 

D28.0

000 11100

001110

1011

001110

0100

 

D28.1

001

11100

001110 1001

001110 1001

 

D29.0

000 11101

101110

0100

010001

1011

 

D29.1

001

11101

101110 1001

010001 1001

 

D30.0

000 11110

011110

0100

100001

1011

 

D30.1

001

11110

011110 1001

100001 1001

 

D31.0

000 11111

101011

0100

010100

1011

 

D31.1

001

11111

101011 1001

010100 1001

 

Document #: 38-02097 Rev. *B

 

 

 

 

 

 

 

 

 

Page 38 of 44

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit PLL Clock Multiplier Transmit BistTransmit Modes CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it