Cypress manual CYV15G0404DXB Transceiver Logic Block Diagram

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CYV15G0404DXB

The CYV15G0404DXB satisfies the SMPTE-259M and SMPTE-292M compliance according to SMPTE EG34-1999 Pathological Test Requirements.

As a second generation HOTLink device, the CYV15G0404DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial link compatibility (data, command, and BIST) with other HOTLink devices. The transmit (TX) section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts either 8-bit data characters or preencoded 10-bit transmission characters. Data characters may be passed from the transmit input register to an integrated 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL (PECL) compatible differential transmission-line drivers at a bit rate of either 10 or 20 times the input reference clock for that channel.

The receive (RX) section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte wide channels. Each channel accepts a serial bit stream from one of two PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. Each recovered bit stream is deserialized and framed into characters,

8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system.

The integrated 8B/10B encoder or decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

The parallel IO interface may be configured for numerous forms of clocking to provide the highest flexibility in system archi- tecture. In addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock.

Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at speed testing of the high speed serial data paths in each transmit and receive section, and across the interconnecting links.

The CYV15G0404DXB is ideal for port applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers and switchers.

CYV15G0404DXB Transceiver Logic Block Diagram

 

TXDA[7:0] TXCTA[1:0]

 

REFCLKA±

RXDA[7:0] RXSTA[2:0]

 

 

 

 

TXDB[7:0] TXCTB[1:0]

 

REFCLKB±

RXDB[7:0] RXSTB[2:0]

 

 

 

 

TXDC[7:0] TXCTC[1:0]

 

REFCLKC±

RXDC[7:0] RXSTC[2:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x10

 

 

 

x11

 

 

 

 

x10

 

 

 

x11

 

 

 

 

x10

 

 

 

x11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXDD[7:0] TXCTD[1:0]

 

REFCLKD±

RXDD[7:0] RXSTD[2:0]

 

 

 

 

 

 

 

 

 

 

 

x10

 

 

 

x11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase

 

Elasticity

 

Align

 

 

Buffer

 

Buffer

 

 

 

 

 

 

 

 

 

 

Encoder

 

Decoder

 

 

8B/10B

 

8B/10B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Framer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serializer

 

Deserializer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TX

 

 

 

RX

 

 

 

 

 

 

 

 

 

 

 

 

Phase

 

Elasticity

 

 

Align

 

 

 

 

Buffer

 

 

Buffer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Encoder

 

Decoder

 

 

 

8B/10B

 

8B/10B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Framer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serializer

 

Deserializer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TX

 

 

 

RX

 

 

 

 

 

 

 

 

 

 

 

 

Phase

 

Elasticity

Align

 

 

Buffer

Buffer

 

 

 

Encoder

 

Decoder

8B/10B

 

8B/10B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Framer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serializer

 

Deserializer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TX

 

 

 

RX

 

 

 

 

 

 

 

 

Phase

 

Elasticity

Align

 

 

Buffer

Buffer

 

 

 

 

 

 

 

 

 

 

 

 

Encoder

 

Decoder

8B/10B

 

8B/10B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Framer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serializer

 

Deserializer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TX

 

 

 

RX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTA1±

OUTA2±

INA1± INA2±

OUTB1±

OUTB2±

INB1± INB2±

OUTC1±

OUTC2±

INC1± INC2±

OUTD1±

OUTD2±

IND1± IND2±

Document #: 38-02097 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit PLL Clock Multiplier Transmit BistTransmit Modes CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it
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