Cypress CYV15G0404DXB manual Reclocker, Clock/Data Recovery, Deserializer/Framer

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CYV15G0404DXB

Transition Density

The transition detection logic checks for the absence of transi- tions spanning greater than six transmission characters (60 bits). If no transitions are present in the data received, the detection logic for that channel asserts LFIx.

Range Controls

The CDR circuit includes logic to monitor the frequency of the PLL Voltage Controlled Oscillator (VCO) used to sample the incoming data stream. This logic ensures that the VCO operates at, or near the rate of the incoming data stream for two primary cases:

■When the incoming data stream resumes after a time in which it has been “missing.”

■When the incoming data stream is outside the acceptable signaling rate range.

To perform this function, the frequency of the RXPLL VCO is periodically compared to the frequency of the REFCLKx± input.

If the VCO is running at a frequency beyond ±1500 ppm, as defined by the REFCLKx± frequency, it is periodically forced to the correct frequency (as defined by REFCLKx±, SPDSELx, and TXRATEx) and then released in an attempt to lock to the input data stream.

The sampling and relock period of the range control is calculated

in the following manner: RANGE_CONTROL_

SAMPLING_PERIOD = (RECOVERED BYTE CLOCK PERIOD) * (4096).

During the time that the range control forces the RXPLL VCO to track REFCLKx±, the LFIx output is asserted LOW. After a valid serial data stream is applied, it may take up to one RANGE CONTROL SAMPLING PERIOD before the PLL locks to the input data stream, after which LFIx should be HIGH.

Receive Channel Enabled

The CYV15G0404DXB contains four receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. When the RXPLLPDx latch = 0, the associated PLL and analog circuitry of the channel is disabled. Any disabled channel indicates a constant link fault condition on the LFIx output. When RXPLLPDx = 1, the associated PLL and receive channel is enabled to receive and decode a serial stream.

Each CDR accepts a character rate (bit-rate ÷ 10) or half-character rate (bit-rate ÷ 20) reference clock from the associated REFCLKx± input. This REFCLKx± input is used to

■Ensure that the VCO (within the CDR) is operating at the correct frequency (rather than a harmonic of the bit-rate)

■Reduce PLL acquisition time

■Limit unlocked frequency excursions of the CDR VCO when there is no input data present at the selected serial line receiver.

Regardless of the type of signal present, the CDR attempts to recover a data stream from it. If the signalling rate of the recovered data stream is outside the limits set by the range control monitors, the CDR tracks REFCLKx± instead of the data stream. Once the CDR output (RXCLK±) frequency returns close to REFCLKx± frequency, the CDR input is switched back to the input data stream. If no data is present at the selected line receiver, this switching behavior may result in brief RXCLK± frequency excursions from REFCLKx±. However, the validity of the input data stream is indicated by the LFIx output. The frequency of REFCLKx± is required to be within ±1500 ppm of the frequency of the clock that drives the REFCLKx± input of the remote transmitter to ensure a lock to the incoming data stream.

For systems using multiple or redundant connections, the LFIx can be output to select an alternate data stream. When an LFIx indication is detected, external logic can toggle selection of the associated INx1± and INx2± input through the associated INSELx input. When a port switch takes place, it is necessary for the receive PLL for that channel to reacquire the new serial stream and frame to the incoming character boundaries.

Reclocker

The CYV15G0404DXB contains a reclocker mode on each receive channel that can be independently enabled and disabled. When the reclocker mode is enabled by RCLKENx, the received serial data is reclocked and transmitted through the enabled differential serial outputs of the selected channel. In the reclocker mode, the RXPLL performs clock and data recovery functions on the input serial data stream and the reclocked serial data is routed to the enabled differential serial outputs. The serial data is also routed to the deserializer and the deserialized data is presented to the RXDx[7:0] and RXSTA[2:0] parallel data outputs as configured by DECBYPx. When the reclocker is enabled, the data on the TXDx[7:0] and TXCT[1:0] is ignored and not transmitted through the enabled serial outputs.

Note. When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms.

Clock/Data Recovery

The extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate CDR block within each receive channel. The clock extraction function is performed by an integrated PLL that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit rate clock to the transitions in the selected serial data stream.

Deserializer/Framer

Each CDR circuit extracts bits from the associated serial data stream and clocks these bits into the shifter/framer at the bit clock rate. When enabled, the framer examines the data stream looking for one or more COMMA or K28.5 characters at all possible bit positions. The location of this character in the data stream determines the character boundaries of all following characters.

Framing Character

The CYV15G0404DXB allows selection of different framing characters on each channel. Two combinations of framing characters are supported to meet the requirements of different interfaces. The selection of the framing character is made

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverName Characteristics Signal Description Status SignalsReceive Path Clock Signals Device Control SignalsUse Local Clock . When Link Fault Indication Output Device Configuration and Control Bus SignalsControl Write Enable . Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit Modes Transmit BistTransmit PLL Clock Multiplier Signal Detect/Link Fault Serial Output DriversCYV15G0404DXB Receive Data Path Serial Line ReceiversReclocker Clock/Data RecoveryDeserializer/Framer 10B/8B Decoder Block Receive Bist OperationBits Detected FramerPower Control Device Reset StateOutput Bus Receive Elasticity BufferDevice Configuration and Control Interface Output Register Bit Assignments Signal NameDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxcksela RxckselbRxckselc RxckseldTxratea TxratebTxratec TxratedDevice Configuration Strategy Device Control Latch Configuration TableRequired step Jtag SupportRunning disparity error . The character on Level Select InputsNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBistdatacompare 000 / Bistcommandcompare BisterrorBiststart RX PLLCYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating RangePower Supply Typ AC Test Loads and WaveformsCML Output Test Load Lvttl Output Test Load18CYV15G0404DXB AC Electrical Characteristics Receiver Lvttl Switching Characteristics Over the OperatingREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitBus Configuration Write Timing Characteristics Over Jtag Test Clock Characteristics Over the Operating RangeTransmit Serial Outputs and TX PLL Characteristics Over DeviceCYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitTransmit Interface Write Timing REFCLKx selectedTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing VCC Power Reset Lvttl in PUCML Lvttl in PURXDC7 Lvttl OUT TXDB6 LvttlTXDC0 Lvttl RXDC4 Lvttl OUTX3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission OrderCode Violations Resulting from Prior Errors Use of the Tables for Generating Transmission CharactersValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Package Diagram Ordering InformationCYV15G0404DXB-BGC CYV15G0404DXB-BGINew Data Sheet AGTUKK/VED Methods to implement it
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