Cypress CYV15G0404DXB manual Transmit Interface, Write Timing REFCLKx selected, TXDx70, TXCTx10

Page 31

CYV15G0404DXB

CYV15G0404DXB HOTLink II Transmitter Switching Waveforms (continued)

Transmit Interface

tREFCLK

 

 

Write Timing

 

 

REFCLKx selected

tREFH

tREFL

 

TXRATEx = 1

 

REFCLKx

Note 33

 

 

 

 

 

 

t

tTREFDH

tTREFDS

TXDx[7:0],

TREFDS

 

 

 

 

TXCTx[1:0],

 

 

 

Note

 

 

 

tTREFDH

33.When REFCLKx± is configured for half rate operation (TXRATE = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx.

Transmit Interface

TXCLKOx Timing

TXRATEx = 1

REFCLKx

Note 35

TXCLKOx (internal)

 

tREFCLK

tREFH

tREFL

 

Note 34

tTXCLKO

 

Transmit Interface TXCLKOx Timing

TXRATEx = 0

REFCLKx

Note 35

tREFCLK

tREFH tREFL

Note 34

tTXCLKO

tTXOH tTXOL

TXCLKOx

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock SignalsUse Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable .CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data PathReclocker Clock/Data RecoveryDeserializer/Framer Framer 10B/8B Decoder BlockReceive Bist Operation Bits DetectedReceive Elasticity Buffer Power ControlDevice Reset State Output BusDECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit NameName Signal Description Device Configuration and Control Latch DescriptionsRxckseld RxckselaRxckselb RxckselcTxrated TxrateaTxrateb TxratecJtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required stepReceive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid DataRX PLL Bistdatacompare 000 / BistcommandcompareBisterror BiststartOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsLvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test LoadParameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating RangeDevice Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics OverParameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CMLRXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 LvttlTransmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeHex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte NameAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGCMethods to implement it New Data SheetAGT UKK/VED
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