Cypress CYV15G0404DXB manual Device Configuration and Control Block, = Internal Signal

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CYV15G0404DXB

Device Configuration and Control Block							= Internal Signal

WREN ADDR[3:0] DATA[7:0]

Device Configura-

tion and Control

Interface

RFMODE[A..D][1:0]

RFEN[A..D]

FRAMCHAR[A..D]

DECMODE[A..D]

RXBIST[A..D]

RXCKSEL[A..D]

DECBYP[A..D]

RXRATE[A..D]

SDASEL[A..D][1:0]

RXPLLPD[A..D]

TXRATE[A..D]

TXCKSEL[A..D]

PABRST[A..D]

TXBIST[A..D]

OE[A..D][2..1]

ENCBYP[A..D]

GLEN[11..0] FLEN[2..0]

Document #: 38-02097 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit PLL Clock Multiplier Transmit BistTransmit Modes Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it