Cypress CYV15G0404DXB Biststart, Rx Pll, Bistdatacompare 000 / Bistcommandcompare, Bisterror

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CYV15G0404DXB

Figure 2. Receive BIST State Machine

 

 

 

 

 

 

 

 

 

 

Monitor Data

 

 

 

 

 

 

 

 

 

 

Received

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXSTx

=

RXSTx

=

 

 

 

 

BIST_WAIT

(111)

BIST_START

(101)

 

 

 

 

 

 

 

 

 

 

 

 

Elasticity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Yes

 

 

Buffer Error

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXSTx =

BIST_START (101)

Receive BIST

 

 

Detected LOW

 

RX PLL

 

 

 

Out of Lock

 

 

Start of

No

No

BIST Detected

Yes, RXSTx =

BIST_DATA_COMPARE (000) / BIST_COMMAND_COMPARE (001)

 

 

Compare

 

 

 

 

Next Character

 

RXSTx =

 

Mismatch

 

 

 

 

 

 

Match BIST_COMMAND_COMPARE (001)

 

Auto-Abort

 

 

Data or

Command

Yes

 

 

Command

 

Condition

 

 

 

 

 

 

 

 

 

No

 

 

 

RXSTx =

 

 

 

Data

BIST_DATA_COMPARE (000)

 

End-of-BIST

 

 

End-of-BIST

No

 

State

 

 

State

 

 

Yes, RXSTx =

 

 

Yes, RXSTx =

 

 

BIST_LAST_BAD (100)

 

 

 

BIST_LAST_GOOD (010)

 

 

 

 

 

No, RXSTx =

 

 

 

 

BIST_ERROR (110)

 

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversReclocker Clock/Data RecoveryDeserializer/Framer Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it
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