Cypress manual Capacitance20, CYV15G0404DXB HOTLink II Transmitter Switching Waveforms

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CYV15G0404DXB

CYV15G0404DXB AC Electrical Characteristics (continued)

Parameter	Description		Min.	Max	Unit
tRISE[20]	CML Output Rise Time 20−80% (CML Test Load)	SPDSELx = HIGH	60	270	ps
		SPDSELx = MID	100	500	ps

		SPDSELx =LOW	180	1000	ps

tFALL[20]	CML Output Fall Time 80−20% (CML Test Load)	SPDSELx = HIGH	60	270	ps
		SPDSELx = MID	100	500	ps

		SPDSELx =LOW	180	1000	ps

tDJ [20, 29, 31]	Deterministic Jitter (peak-peak)[32]	IEEE 802.3z		27	ps
Z [20, 30, 31]	Random Jitter (σ)[32]	IEEE 802.3z		11	ps
RJ
tREFJ[20]	REFCLKx jitter tolerance / Phase noise limits			TBD
tTXLOCK	Transmit PLLx lock to REFCLKx±			200	μs
CYV15G0404DXB	Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
tRXLOCK	Receive PLL lock to input data stream (cold start)			376k	UI
	Receive PLL lock to input data stream			376k	UI

tRXUNLOCK	Receive PLL Unlock Rate			46	UI
tJTOL[20]	Total Jitter Tolerance[32]	IEEE 802.3z	600		ps
tDJTOL[20]	Deterministic Jitter Tolerance[32]	IEEE 802.3z	370		ps

Capacitance[20]

Parameter	Description	Test Conditions	Max.	Unit
CINTTL	TTL Input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	7	pF
CINPECL	PECL input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	4	pF

CYV15G0404DXB HOTLink II Transmitter Switching Waveforms

Transmit Interface

Write Timing

TXCLKx selected

TXCLKx

TXDx[7:0],

TXCTx[1:0],

Transmit Interface

Write Timing

REFCLKx selected

TXRATEx = 0

REFCLKx

TXDx[7:0],

TXCTx[1:0],

	tTXCLK
tTXCLKH	tTXCLKL
	tTXDS	tTXDH

tREFCLK

tREFH tREFL

tTREFDS						t


						TREFDH

Document #: 38-02097 Rev. *B

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit Bist Transmit ModesTransmit PLL Clock Multiplier CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversClock/Data Recovery ReclockerDeserializer/Framer Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it