Cypress CYV15G0404DXB manual Encoder, Data Encoding

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CYV15G0404DXB

Once initialized, TXCLKx is allowed to drift in phase as much as ±180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity of the phase align buffer, TXERRx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. The phase of the TXCLKx relative to its associated internal character rate clock is initialized when the configuration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the phase align buffer is initialized and input characters are correctly captured.

Table 1. Input Register Bit Assignments[7]

Signal Name

Unencoded

Encoded

TXDx[0] (LSB)

DINx[0]

TXDx[0]

 

 

 

TXDx[1]

DINx[1]

TXDx[1]

 

 

 

TXDx[2]

DINx[2]

TXDx[2]

 

 

 

TXDx[3]

DINx[3]

TXDx[3]

 

 

 

TXDx[4]

DINx[4]

TXDx[4]

 

 

 

TXDx[5]

DINx[5]

TXDx[5]

 

 

 

TXDx[6]

DINx[6]

TXDx[6]

 

 

 

TXDx[7]

DINx[7]

TXDx[7]

 

 

 

TXCTx[0]

DINx[8]

TXCTx[0]

 

 

 

TXCTx[1] (MSB)

DINx[9]

TXCTx[1]

 

 

 

Note

7. LSB shifted out first.

If the phase offset between the initialized location of the input clock and REFCLKx exceeds the skew handling capabilities of the phase align buffer, an error is reported on that channel’s TXERRx output. This output indicates an error continuously until the phase align buffer for that channel is reset. While the error remains active, the transmitter for that channel outputs a continuous C0.7 character to indicate to the remote receiver that an error condition is present in the link.

Each phase align buffer may be individually reset with minimal disruption of the serial data stream. When a phase align buffer error is present, the transmission of a word sync sequence recenters the phase align buffer and clears the error indication.

Note. K28.5 characters may be added or removed from the data stream during the phase align buffer reset operation. When used with non-Cypress devices that require a complete 16-character word sync sequence for proper receive elasticity buffer operation, follow the phase alignment buffer reset by a word sync sequence to ensure proper operation.

Encoder

Each character received from the Input register or phase align buffer is passed to the encoder logic. This block interprets each character and any associated control bits, and outputs a 10-bit transmission character.

Depending on the operational mode, the generated transmission character may be

■The 10-bit preencoded character accepted in the input register.

■The 10-bit equivalent of the 8-bit Data character accepted in the input register

■The 10-bit equivalent of the 8-bit Special Character code accepted in the input register

■The 10-bit equivalent of the C0.7 violation character if a phase align buffer overflow or underflow error is present

■A character that is part of the 511-character BIST sequence

■A K28.5 character generated as an individual character or as part of the 16-character Word Sync Sequence

Data Encoding

Raw data, as received directly from the transmit input register, is seldom in a form suitable for transmission across a serial link. The characters must usually be processed or transformed to guarantee

■a minimum transition density (to allow the receive PLL to extract a clock from the serial data stream)

■A DC-balance in the signaling (to prevent baseline wander)

■Run length limits in the serial data (to limit the bandwidth requirements of the serial link)

■the remote receiver a way of determining the correct character boundaries (framing)

When the encoder is enabled (ENCBYPx = 1), the characters transmitted are converted from data or special character codes to 10-bit transmission characters, using an integrated 8B/10B encoder. When directed to encode the character as a special character code, the encoder uses the special character encoding rules listed in Table 15. When directed to encode the character as a data character, it is encoded using the data character encoding rules in Table 14.

The 8B/10B encoder is standards compliant with ANSI/NCITS ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit Ethernet, the IBM® ESCON® and FICON™ channels, ETSI DVB-ASI, and ATM Forum standards for data transport.

Many of the special character codes listed in Table 15 may be generated by more than one input character. The CYV15G0404DXB is designed to support two independent (but non-overlapping) special character code tables. This allows the CYV15G0404DXB to operate in mixed environments with other Cypress HOTLink devices using the enhanced Cypress command code set, and the reduced command sets of other non-Cypress devices. Even when used in an environment that normally uses non-Cypress Special Character codes, the selective use of Cypress command codes can permit operation where running disparity and error handling must be managed.

Following conversion of each input character from eight bits to a 10-bit transmission character, it is passed to the transmit shifter and is shifted out LSB first, as required by ANSI and IEEE standards for 8B/10B coded serial data streams.

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversReclocker Clock/Data RecoveryDeserializer/Framer Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it
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