Cypress CYV15G0404DXB manual Data Bits Current RD Current RD+ Byte Name

Page 39

CYV15G0404DXB

Table 14.

Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

Bits

Current RD

Current RD+

 

Data

Bits

Current RD+

 

Byte

 

 

Byte

Current RD

 

Name

HGF EDCBA

abcdei fghj

abcdei fghj

 

Name

HGF EDCBA

abcdei fghj

abcdei fghj

 

D0.2

010 00000

100111

0101

011000

0101

 

D0.3

011 00000

100111 0011

011000 1100

 

D1.2

010 00001

011101

0101

100010

0101

 

D1.3

011 00001

011101 0011

100010 1100

 

D2.2

010 00010

101101

0101

010010

0101

 

D2.3

011 00010

101101 0011

010010 1100

 

D3.2

010 00011

110001

0101

110001

0101

 

D3.3

011 00011

110001 1100

110001 0011

 

D4.2

010 00100

110101

0101

001010

0101

 

D4.3

011 00100

110101 0011

001010 1100

 

D5.2

010 00101

101001

0101

101001

0101

 

D5.3

011 00101

101001 1100

101001 0011

 

D6.2

010 00110

011001

0101

011001

0101

 

D6.3

011 00110

011001 1100

011001 0011

 

D7.2

010 00111

111000

0101

000111

0101

 

D7.3

011 00111

111000 1100

000111 0011

 

D8.2

010 01000

111001

0101

000110

0101

 

D8.3

011 01000

111001 0011

000110 1100

 

D9.2

010 01001

100101

0101

100101

0101

 

D9.3

011 01001

100101 1100

100101 0011

 

D10.2

010 01010

010101

0101

010101

0101

 

D10.3

011

01010

010101 1100

010101 0011

 

D11.2

010 01011

110100

0101

110100

0101

 

D11.3

011

01011

110100 1100

110100 0011

 

D12.2

010 01100

001101

0101

001101

0101

 

D12.3

011

01100

001101 1100

001101 0011

 

D13.2

010 01101

101100

0101

101100

0101

 

D13.3

011

01101

101100 1100

101100 0011

 

D14.2

010 01110

011100

0101

011100

0101

 

D14.3

011

01110

011100 1100

011100 0011

 

D15.2

010 01111

010111

0101

101000

0101

 

D15.3

011

01111

010111 0011

101000 1100

 

D16.2

010 10000

011011

0101

100100

0101

 

D16.3

011

10000

011011 0011

100100 1100

 

D17.2

010 10001

100011

0101

100011

0101

 

D17.3

011

10001

100011 1100

100011 0011

 

D18.2

010 10010

010011

0101

010011

0101

 

D18.3

011

10010

010011 1100

010011 0011

 

D19.2

010 10011

110010

0101

110010

0101

 

D19.3

011

10011

110010 1100

110010 0011

 

D20.2

010 10100

001011

0101

001011

0101

 

D20.3

011

10100

001011 1100

001011 0011

 

D21.2

010 10101

101010

0101

101010

0101

 

D21.3

011

10101

101010 1100

101010 0011

 

D22.2

010 10110

011010

0101

011010

0101

 

D22.3

011

10110

011010 1100

011010 0011

 

D23.2

010 10111

111010

0101

000101

0101

 

D23.3

011

10111

111010 0011

000101 1100

 

D24.2

010 11000

110011

0101

001100

0101

 

D24.3

011

11000

110011 0011

001100 1100

 

D25.2

010 11001

100110

0101

100110

0101

 

D25.3

011

11001

100110 1100

100110 0011

 

D26.2

010 11010

010110

0101

010110

0101

 

D26.3

011

11010

010110 1100

010110 0011

 

D27.2

010 11011

110110

0101

001001

0101

 

D27.3

011

11011

110110 0011

001001 1100

 

D28.2

010 11100

001110

0101

001110

0101

 

D28.3

011

11100

001110 1100

001110 0011

 

D29.2

010 11101

101110

0101

010001

0101

 

D29.3

011

11101

101110 0011

010001 1100

 

D30.2

010 11110

011110

0101

100001

0101

 

D30.3

011

11110

011110 0011

100001 1100

 

D31.2

010 11111

101011

0101

010100

0101

 

D31.3

011

11111

101011 0011

010100 1100

 

Document #: 38-02097 Rev. *B

 

 

 

 

 

 

 

 

 

Page 39 of 44

[+] Feedback

Image 39
Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock SignalsUse Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable .CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Bist Transmit ModesTransmit PLL Clock Multiplier Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data PathClock/Data Recovery ReclockerDeserializer/Framer Framer 10B/8B Decoder BlockReceive Bist Operation Bits DetectedReceive Elasticity Buffer Power ControlDevice Reset State Output BusDECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit NameName Signal Description Device Configuration and Control Latch DescriptionsRxckseld RxckselaRxckselb RxckselcTxrated TxrateaTxrateb TxratecJtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required stepReceive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid DataRX PLL Bistdatacompare 000 / BistcommandcompareBisterror BiststartOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsLvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test LoadParameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating RangeDevice Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics OverParameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CMLRXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 LvttlTransmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeHex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte NameAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGCMethods to implement it New Data SheetAGT UKK/VED