Cypress CY8CNP102B, CY8CNP102E manual Overview, Features

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PRELIMINARY CY8CNP102B, CY8CNP102E

Nonvolatile Programmable System-on-Chip

(PSoC® NV)

Overview

The Cypress nonvolatile Programmable System-on-Chip (PSoC® NV) processor combines a versatile Programmable System-on-Chip™ (PSoC) core with an infinite endurance nvSRAM in a single package. The PSoC NV combines an 8-bit MCU core (M8C), configurable analog and digital functions, a uniquely flexible IO interface, and a high density nvSRAM. This creates versatile data logging solutions that provide value through component integration and programmability. The flexible core and a powerful development environment work to reduce design complexity, component count, and development time.

Features

■Powerful Harvard Architecture Processor

❐M8C processor speeds

•Up to 12 MHz for 3.3V operation

•Up to 24 MHz for 5V operation

❐Two 8x8 multiply, 32 bit accumulate

❐Low power at high speed

■Operating Voltage

❐3.3V (CY8CNP102B)

❐5V (CY8CNP102E)

■Advanced Peripherals

❐12 Rail-to-Rail Analog PSoC blocks provide:

•Up to 14 bit ADCs

•Up to 9 bit DACs

•Programmable Gain Amplifiers

•Programmable Filters and Comparators

•8 Analog channels for simultaneous sampling

•Up to 820 SPS for each channel with 8 channel sampling and logging

❐16 Digital PSoC Blocks provide:

•8 to 32 bit timers, counters, and PWMs

•CRC and PRS Modules

•Up to 4 Full Duplex UARTs

•Multiple SPI™ Masters and Slaves

❐Complex Peripherals by Combining Blocks

■Precision, Programmable Clocking

❐Internal ±2.5% 24 and 48 MHz Oscillator

❐24 and 48 MHz with optional 32.768 kHz Crystal

❐Optional External Oscillator, up to 24 MHz

❐Internal Oscillator for Watchdog and Sleep

■Flexible On-Chip Memory

❐32K Bytes Flash Program Storage

❐2K Bytes SRAM Data Storage

❐256K Bytes secure store nvSRAM with data throughput be- tween 100 KBPS and 1 MBPS

❐In-System Serial Programming (ISSP)

❐Partial Flash Updates

❐Flexible Protection Modes

❐EEPROM Emulation in Flash

■Programmable Pin Configurations

❐33 GPIOs

❐25 mA Sink on all GPIO

❐Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO

❐Up to 12 Analog Inputs on GPIOs

❐Analog Outputs with 40 mA on 4 GPIOs

❐Configurable Interrupt on all GPIOs

■Additional System Resources

❐I2C Slave, Master, and MultiMaster to 100 Kbps and 400 Kbps

❐Watchdog and Sleep Timers

❐Integrated Supervisory Circuit

❐On-Chip Precision Voltage Reference

■Complete Development Tools

❐Free Development Software (PSoC Designer™)

❐Full Featured, In Circuit Emulator and Programmer

❐Full Speed Emulation

❐C Compilers, Assembler, and Linker

■Temperature and Packaging

❐Industrial Temperature Range: -40°C to +85°C

❐Packaging: 100-pin TQFP

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 001-43991 Rev. *D

 

Revised October 20, 2008

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Contents Overview FeaturesLogic Block Diagram Gpio PinoutsENW NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bVerify Output Low Voltage During Programming orBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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