Cypress CY8CNP102E, CY8CNP102B manual Package Diagrams, Thermal Impedance, Tqfp, 81 oC/W

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PRELIMINARY CY8CNP102B, CY8CNP102E

Packaging Information

This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package.

Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161.

Package Diagrams

Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm

51-85048 *C

Thermal Impedance

Table 41. Thermal Impedance

 

 

 

 

 

Package[10]

Typical θJA *

Typical θJC *

100 TQFP

26.14 oC/W

5.81 oC/W

Note

10. * TJ = TA + POWER x θJA

Document #: 001-43991 Rev. *D

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Contents Features OverviewLogic Block Diagram Pinouts GpioENW NVW NVA1NVA2 ENA1PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM OperationProgrammable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per secondOperating Temperature 3V OperationAbsolute Maximum Ratings ESDDC Electrical Characteristics Cmrroa PsrroaPsrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimeVdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bSupply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistorAC Electrical Characteristics DC24MPower Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Crcprs SpimSpis BwobData Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 toInput Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100bOutput Low Voltage During Programming or VerifyBlock Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHzMHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l eExternal Crystal Oscillator Startup Timing Diagram L e c tPart Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXIPackage Diagrams Thermal ImpedanceTqfp 81 oC/WDocument History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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