Cypress CY8CNP102E, CY8CNP102B manual Designing with User Modules, Hardware Tools

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PRELIMINARY CY8CNP102B, CY8CNP102E

Online Help System

The online help system displays online, context sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC through the USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed

(24 MHz) operation.

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that manages specification change during development and lowers inventory costs. These configurable resources, called PSoC Blocks, implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of selecting a different part to meet the final design requirements.

To speed the development process, the PSoC Designer IDE provides a library of prebuilt, pretested hardware peripheral functions, called “User Modules.” User modules simplify selecting and implementing peripheral devices, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 peripherals such as ADCs, DACs, Timers, Counters, UARTs, nvSRAM, DTMF Generators, and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that enable you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module Application Programming Interface (API) provides high level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, which is a graphical user interface (GUI) for configuring the hardware. Pick the user modules required for your project and map them onto the PSoC blocks with point and click simplicity. Next, build signal chains by interconnecting user modules to each other and to the IO pins. At this stage, configure the clock source connections and enter parameter values directly or by selecting values from drop down menus. When you are ready to test the hardware configuration or develop code for the project, perform the “Generate Application” step. PSoC Designer generates source code that automatically configures the device to your specification and provides high level user module API functions.

User Module and Source Code Development Flows

The next step is to write the main program, and any subroutine using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that enables you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager.

It employs a professional strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. After correction, the linker builds a HEX file image suitable for programming.

Figure 3. User Module and Source Code Development Flows

 

 

 

Device Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

User

 

 

Placement

 

 

Source

 

 

 

 

 

 

and

 

 

 

 

 

 

Module

 

 

 

 

Code

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

Selection

 

 

 

 

Generator

 

 

 

 

 

 

-ization

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Generate

Application

Application Editor

Project

 

Source

 

Build

 

Code

 

Manager

 

 

Manager

 

Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Build

 

 

 

 

 

 

All

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Debugger

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interface

 

Storage

 

Event &

 

 

 

 

 

Breakpoint

 

 

 

to ICE

 

Inspector

 

 

 

 

 

 

 

 

 

 

 

Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 001-43991 Rev. *D

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Contents Features OverviewLogic Block Diagram ENW PinoutsGpio NVW NVA1NVA2 ENA1PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM OperationAdditional System Resources Programmable Digital SystemProgrammable Analog System Esigner Development ToolsPSoC Designer Software Subsystems User Module and Source Code Development Flows Designing with User ModulesHardware Tools Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per secondOperating Temperature 3V OperationAbsolute Maximum Ratings ESDDC Electrical Characteristics Cmrroa PsrroaPsrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimeVdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bSupply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistorAC Electrical Characteristics DC24MPower Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Crcprs SpimSpis BwobData Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 toInput Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100bBlock Output Low Voltage During Programming orVerify Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHzMHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l eExternal Crystal Oscillator Startup Timing Diagram L e c tPart Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXIPackage Diagrams Thermal ImpedanceTqfp 81 oC/WGVCH/PYRS Document HistoryPyrs USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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