Cypress CY8CNP102B manual Gpio Operating Frequency, MHz Normal Strong Mode TRiseF, Vcc = 4.75V to

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PRELIMINARY CY8CNP102B, CY8CNP102E

In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place. Industrial grade devices require 15 ms maximum.

Table 34. 5V nvSRAM AutoStore/Power Up RECALL (CY8CNP102E)

Parameter

 

Description

 

 

 

 

 

nvSRAM

 

Unit

 

 

 

 

 

Min

 

 

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

tHRECALL

 

Power Up RECALL Duration

 

 

 

 

 

 

 

20

 

ms

tSTORE

 

STORE Cycle Duration

 

 

 

 

 

 

 

12.5

 

ms

VSWITCH

 

Low Voltage Trigger Level

 

 

 

 

 

 

 

4.4

 

V

tVccRISE

 

VCC Rise Time

 

 

 

 

150

 

 

 

 

μs

AC General Purpose IO Specifications

 

 

 

 

 

 

 

 

 

 

Table 35. 5V AC GPIO Specifications (CY8CNP102E)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Description

Min

Typ

 

Max

Units

 

Notes

FGPIO

 

GPIO Operating Frequency

0

 

12.3

MHz

Normal Strong Mode

TRiseF

 

Rise Time, Normal Strong Mode, Cload = 50 pF

3

 

18

ns

Vcc = 4.75V to 5.25V

 

 

 

 

 

 

 

 

 

 

 

10% - 90%

 

 

TFallF

 

Fall Time, Normal Strong Mode, Cload = 50 pF

2

 

18

ns

Vcc = 4.75V to 5.25V

 

 

 

 

 

 

 

 

 

 

 

10% - 90%

 

 

 

 

 

Figure 7. GPIO Timing Diagram

 

 

 

 

 

 

90%

GPIO

Pin

Output

Voltage

10%

TRiseF

TFallF

TRiseS

TFallS

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram ENW PinoutsGpio NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationAdditional System Resources Programmable Digital SystemProgrammable Analog System Esigner Development ToolsPSoC Designer Software Subsystems User Module and Source Code Development Flows Designing with User ModulesHardware Tools Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bBlock Output Low Voltage During Programming orVerify MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WGVCH/PYRS Document HistoryPyrs USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions