Cypress CY8CNP102E DC Analog Reference Specifications, Agnd = BandGap1 Agnd = 1.6 x BandGap1

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PRELIMINARY CY8CNP102B, CY8CNP102E

DC Analog Reference Specifications

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Table 10. 3.3V DC Analog Reference Specifications (CY8CNP102B)

Symbol	Description	Min	Typ	Max	Units
VBG33	Bandgap Voltage Reference 3.3V	1.28	1.30	1.32	V
–	AGND = Vcc/2[1]	Vcc/2 - 0.02	Vcc/2	Vcc/2 + 0.02	V
–	AGND = 2 x BandGap[1]		Not Allowed
–	AGND = P2[4] (P2[4] = Vcc/2)	P2[4] - 0.009	P2[4]	P2[4] + 0.009	V

–	AGND = BandGap[1]	1.27	1.30	1.34	V
–	AGND = 1.6 x BandGap[1]	2.03	2.08	2.13	V
–	AGND Block to Block Variation (AGND = Vcc/2)[1]	-0.034	0.000	0.034	mV
–	RefHi = Vcc/2 + BandGap	Not Allowed

–	RefHi = 3 x BandGap	Not Allowed

–	RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)	Not Allowed

–	RefHi = P2[4] + BandGap (P2[4] = Vcc/2)	Not Allowed

–	RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V)	P2[4] + P2[6] - 0.042	P2[4] + P2[6]	P2[4] + P2[6] + 0.042	V

–	RefHi = 2 x BandGap	2.50	2.60	2.70	V

–	RefHi = 3.2 x BandGap	Not Allowed

–	RefLo = Vcc/2 - BandGap	Not Allowed

–	RefLo = BandGap	Not Allowed

–	RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)	Not Allowed

–	RefLo = P2[4] – BandGap (P2[4] = Vcc/2)	Not Allowed

–	RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V)	P2[4] - P2[6] - 0.036	P2[4] - P2[6]	P2[4] - P2[6] + 0.036	V

DC Analog PSoC NV Block Specifications
Table 11. 3.3V DC Analog PSoC NV Block Specifications (CY8CNP102B)

Symbol	Description	Min	Typ	Max	Units
RCT	Resistor Unit Value (Continuous Time)	–	12.2	–	kΩ
CSC	Capacitor Unit Value (Switch Cap)	–	80	–	fF

Note

1. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

Document #: 001-43991 Rev. *D

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Contents Features OverviewLogic Block Diagram ENW PinoutsGpio NVA2 NVWNVA1 ENA1NvSRAM Data Memory PSoC NV Functional OverviewPSoC NV Core NvSRAM OperationAdditional System Resources Programmable Digital SystemProgrammable Analog System Esigner Development ToolsPSoC Designer Software Subsystems User Module and Source Code Development Flows Designing with User ModulesHardware Tools Microhenry Picosecond Microsecond Cypress nvSRAM user ModuleParts per million Samples per secondAbsolute Maximum Ratings Operating Temperature3V Operation ESDDC Electrical Characteristics Cmrroa PsrroaPsrr OB Agnd = BandGap1 Agnd = 1.6 x BandGap1 DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Resistor Unit Value Continuous TimePORLEV10 = 00b Ppor Hysteresis Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00bDriving internal pull Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify During Programming or Verify Down resistorAC Electrical Characteristics DC24MStore Cycle Duration 12.5 Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Low Voltage Trigger LevelBwoa Spis CrcprsSpim BwobSetup Time for a Repeated Start Condition Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Hold Time Data Setup Time5V Operation Combined IOH budget Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Input Low Level 75 toLow power comparator LPC reference voltage range Vcc Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Average Input Offset Voltage DriftPsrrob VM20 = 011b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 100bBlock Output Low Voltage During Programming orVerify See on Using factory trim valuesMHz Trimmed for 5V operation Internal Main Oscillator Frequency for 6 MHzVcc = 4.75V to MHz Normal Strong Mode TRiseFGpio Operating Frequency TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Sions Transmitter Maximum Input Clock Frequency 24.6 MHz Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l eExternal Crystal Oscillator Startup Timing Diagram L e c tCY8CNP102B-AXI Part Numbering NomenclatureOrdering Information CY8CNP102E-AXITqfp Package DiagramsThermal Impedance 81 oC/WGVCH/PYRS Document HistoryPyrs USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions