Cypress CY8CNP102E, CY8CNP102B manual Crcprs, Spim, Spis, Bwob

PRELIMINARY CY8CNP102B, CY8CNP102E

Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued)

Function		Description	Min	Typ	Max	Units		Notes
CRCPRS	Maximum Input Clock Frequency		–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V
(PRS Mode)
CRCPRS	Maximum Input Clock Frequency		–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V.
(CRC Mode)
SPIM	Maximum Input Clock Frequency		–	–	8.2	MHz	Maximum data rate at
							4.1 MHz due to 2 x
							over clocking.
SPIS	Maximum Input Clock Frequency		–	–	4.1	ns
	Width of SS_ Negated Between Transmissions		50[8]	–	–	ns
Transmitter	Maximum Input Clock Frequency		–	–	24.6	MHz	Maximum data rate at
	Vcc ≥ 3.0V, 2 Stop Bits						3.08 MHz due to 8 x
							over clocking.
			–	–	49.2	MHz	Maximum data rate at
							6.15 MHz due to 8 x
							over clocking.
Receiver	Maximum Input Clock Frequency		–	–	24.6	MHz	Maximum data rate at
							3.08 MHz due to 8 x
							over clocking.
	Vcc ≥ 3.0V, 2 Stop Bits		–	–	49.2	MHz	Maximum data rate at
							6.15 MHz due to 8 x
							over clocking.
AC Analog Output Buffer Specifications
Table 19. 3.3V AC Analog Output Buffer Specifications (CY8CNP102B)
Symbol		Description			Min	Typ	Max		Units
TROB		Rising Settling Time to 0.1%, 1V Step, 100pF Load
		Power = Low			–	–	4.7		μs
		Power = High			–	–	4.7		μs
TSOB		Falling Settling Time to 0.1%, 1V Step, 100pF Load
		Power = Low			–	–	4		μs
		Power = High			–	–	4		μs
SRROB		Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
		Power = Low			0.36	–	–		V/μs
		Power = High			0.36	–	–		V/μs
SRFOB		Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
		Power = Low			0.4	–	–		V/μs
		Power = High			0.4	–	–		V/μs
BWOB		Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
		Power = Low			0.7	–	–		MHz
		Power = High			0.7	–	–		MHz
BWOB		Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
		Power = Low			200	–	–		kHz
		Power = High			200	–	–		kHz

Document #: 001-43991 Rev. *D Page 20 of 38

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