Cypress CY8CNP102B, CY8CNP102E manual Development Tools, PSoC Designer Software Subsystems, Esigner

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PRELIMINARY CY8CNP102B, CY8CNP102E

Development Tools

PSoC Designer is a Microsoft® Windows based, integrated development environment for Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application run on Windows NT 4.0, Windows 2000, Windows Millennium (Me), Microsoft Vista, and Windows XP.

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high level C language compiler developed specifically for the devices in this family.

Figure 2. PSoC Designer Subsystem

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PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules, using the PSoC blocks. Examples of user modules are ADCs, DACs, nvSRAM, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time.

PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components. Also, if the project uses more than one operating configuration, the framework contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration, for use during application programming in conjunction with the Device Data Sheet. After the framework is generated, the user can add application specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser enables users to select and import preconfigured designs into their project. Users can easily browse a catalog of preconfigured designs to facilitate time to design. Examples provided in the tools include a 300 baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit C language and Assembly language source code. You can also assemble, compile, link, and build.

Assembler. The macro assembler seamlessly merges the assembly code with C code. The link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler that supports Cypress PSoC family devices is available. Even if you have never worked in the C language before, the product quickly enables you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It is complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, which enables the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands enable the designer to read and program, read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also enables the designer to create a trace buffer of registers and memory locations of interest.

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram Gpio PinoutsENW ENA1 NVWNVA1 NVA2NvSRAM Operation PSoC NV Functional OverviewPSoC NV Core NvSRAM Data MemoryProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Samples per second Cypress nvSRAM user ModuleParts per million Microhenry Picosecond MicrosecondESD Operating Temperature3V Operation Absolute Maximum RatingsDC Electrical Characteristics Psrroa CmrroaPsrr OB Resistor Unit Value Continuous Time DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Agnd = BandGap1 Agnd = 1.6 x BandGap1PORLEV10 = 00b Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00b Ppor HysteresisDuring Programming or Verify Down resistor Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify Driving internal pullDC24M AC Electrical CharacteristicsLow Voltage Trigger Level Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Store Cycle Duration 12.5Bwoa Bwob CrcprsSpim SpisData Hold Time Data Setup Time Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Setup Time for a Repeated Start Condition5V Operation Input Low Level 75 to Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Combined IOH budgetAverage Input Offset Voltage Drift Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Low power comparator LPC reference voltage range VccPsrrob VM20 = 100b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 011bVerify Output Low Voltage During Programming orBlock Internal Main Oscillator Frequency for 6 MHz Using factory trim valuesMHz Trimmed for 5V operation See onTFallF MHz Normal Strong Mode TRiseFGpio Operating Frequency Vcc = 4.75V toMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Sions Transmitter Maximum Input Clock Frequency 24.6 MHzData Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramCY8CNP102E-AXI Part Numbering NomenclatureOrdering Information CY8CNP102B-AXI81 oC/W Package DiagramsThermal Impedance TqfpPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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