Cypress CY8CNP102B, CY8CNP102E manual Pinouts, Gpio, Enw

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PRELIMINARY CY8CNP102B, CY8CNP102E

Pinouts

Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)

Table 1. Pin Definitions - 100-Pin TQFP

Pin Number	Pin Name		Type		Pin Definition
Pin Number	Pin Name	Digital		Analog	Pin Definition
		Digital		Analog
1	P0_5	IO		IO	Analog Column Mux Input and Column Output

2	P0_3	IO		IO	Analog Column Mux Input and Column Output

3	P0_1	IO		I	Analog Column Mux Input, GPIO

4	P2_7	IO			GPIO

5	P2_5	IO			GPIO

6	P2_3	IO		I	Direct Switched Capacitor Block Input

7	P2_1	IO		I	Direct Switched Capacitor Block Input

8	Vcc		Power		Supply Voltage

9	DNU				Reserved for test modes - Do Not Use

10	DNU				Reserved for test modes - Do Not Use

11	DNU				Reserved for test modes - Do Not Use

12	DNU				Reserved for test modes - Do Not Use

13	DNU				Reserved for test modes - Do Not Use

14	NC				Not connected on the die
15	P3_5	IO			GPIO

16	EN_W				Connect to Pin 26 (EN_W to NV_W)

17	P3_1	IO			GPIO

Document #: 001-43991 Rev. *D					Page 3 of 38

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Contents Overview FeaturesLogic Block Diagram Pinouts GpioENW ENA1 NVWNVA1 NVA2NvSRAM Operation PSoC NV Functional OverviewPSoC NV Core NvSRAM Data MemoryProgrammable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Samples per second Cypress nvSRAM user ModuleParts per million Microhenry Picosecond MicrosecondESD Operating Temperature3V Operation Absolute Maximum RatingsDC Electrical Characteristics Psrroa CmrroaPsrr OB Resistor Unit Value Continuous Time DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Agnd = BandGap1 Agnd = 1.6 x BandGap1PORLEV10 = 00b Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00b Ppor HysteresisDuring Programming or Verify Down resistor Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify Driving internal pullDC24M AC Electrical CharacteristicsLow Voltage Trigger Level Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Store Cycle Duration 12.5Bwoa Bwob CrcprsSpim SpisData Hold Time Data Setup Time Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Setup Time for a Repeated Start Condition5V Operation Input Low Level 75 to Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Combined IOH budgetAverage Input Offset Voltage Drift Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Low power comparator LPC reference voltage range VccPsrrob VM20 = 100b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 011bOutput Low Voltage During Programming or VerifyBlock Internal Main Oscillator Frequency for 6 MHz Using factory trim valuesMHz Trimmed for 5V operation See onTFallF MHz Normal Strong Mode TRiseFGpio Operating Frequency Vcc = 4.75V toMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Sions Transmitter Maximum Input Clock Frequency 24.6 MHzData Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramCY8CNP102E-AXI Part Numbering NomenclatureOrdering Information CY8CNP102B-AXI81 oC/W Package DiagramsThermal Impedance TqfpDocument History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

Pinouts

Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)

Table 1. Pin Definitions - 100-Pin TQFP

Pin Number

Pin Name

Type

Digital

Analog

GPIO

EN_W