Cypress CY8CNP102B Rise Time of Sclk, Fall Time of Sclk, Data Set up Time to Falling Edge of Sclk

Page 21

PRELIMINARY CY8CNP102B, CY8CNP102E

AC Programming Specifications

Table 20. 3.3V AC Programming Specifications (CY8CNP102B)

Symbol

Description

Min

Typ

Max

Units

Notes

TRSCLK

Rise Time of SCLK

1

–

20

ns

 

TFSCLK

Fall Time of SCLK

1

–

20

ns

 

TSSCLK

Data Set up Time to Falling Edge of SCLK

40

–

–

ns

 

THSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

 

FSCLK

Frequency of SCLK

0

–

8

MHz

 

TERASEB

Flash Erase Time (Block)

–

10

–

ms

 

TWRITE

Flash Block Write Time

–

10

–

ms

 

TDSCLK3

Data Out Delay from Falling Edge of SCLK

–

–

50

ns

3.0V ≤ Vcc ≤ 3.6V

AC I2C Specifications

Table 21. 3.3V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102B)

Symbol

Description

Standard Mode

Fast Mode

Units

Min

Max

Min

Max

 

 

 

FSCLI2C

SCL Clock Frequency

0

100

0

400

kHz

THDSTAI2C

Hold Time (repeated) START Condition. After this period, the

4.0

–

0.6

–

μs

 

first clock pulse is generated.

 

 

 

 

 

TLOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

THIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

TSUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μs

THDDATI2C

Data Hold Time

0

–

0

–

μs

T

Data Setup Time

250

–

100[9]

–

ns

SUDATI2C

 

 

 

 

 

 

TSUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μs

TBUFI2C

Bus Free Time Between a STOP and START Condition

4.7

–

1.3

–

μs

TSPI2C

Pulse Width of spikes are suppressed by the input filter.

–

–

0

50

ns

Note

9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram Pinouts GpioENW NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationProgrammable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bOutput Low Voltage During Programming or VerifyBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WDocument History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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