Cypress CY8CNP102B, CY8CNP102E High Output Level Vcc, Combined IOH budget, Input Low Level 75 to

Page 23

PRELIMINARY CY8CNP102B, CY8CNP102E

DC Electrical Characteristics

The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

DC Chip Level Specifications

Table 24. 5V DC Chip-Level Specifications (CY8CNP102E)

Symbol

Description

Min

Typ

Max

Units

Notes

Vcc

Supply Voltage

4.75

–

5.25

V

 

 

 

 

 

 

 

 

I

Supply Current

–

39

45

mA

T = 25 oC, CPU = 3 MHz,

DD

 

 

 

 

 

A

 

 

 

 

 

 

SYSCLK doubler disabled,

 

 

 

 

 

 

VC1 = 1.5 MHz, VC2 = 93.75 kHz,

 

 

 

 

 

 

VC3 = 0.366 kHz, continuous

 

 

 

 

 

 

nvSRAM access

I

Supply current when IMO = 6 MHz

–

27

28

mA

T = 25 oC, CPU = 0.75 MHz,

DDP

using SLIMO mode.

 

 

 

 

A

 

 

 

 

 

SYSCLK doubler disabled,

 

 

 

 

 

 

VC1=0.375 MHz, VC2=23.44

 

 

 

 

 

 

kHz, VC3 = 0.09 kHz, continuous

 

 

 

 

 

 

nvSRAM access

ISB

Sleep (Mode) Current with POR,

–

–

5

mA

nvSRAM in standby.

 

LVD, Sleep Timer, WDT, and

 

 

 

 

 

 

internal slow oscillator active.

 

 

 

 

 

VREF

Reference Voltage (Bandgap)

1.28

1.3

1.32

V

Trimmed for appropriate Vcc.

Vcap

Storage Capacitor between Vcap

61

68

82

uF

5V rated (minimum)

 

and Vss

 

 

 

 

 

DC General Purpose IO Specifications

 

 

 

 

 

Table 25. 5V DC GPIO Specifications (CY8CNP102E)

 

 

 

 

 

 

 

 

 

 

 

Symbol

Description

Min

Typ

Max

Units

Notes

RPU

Pull up Resistor

4

5.6

8

kΩ

 

RPD

Pull down Resistor

4

5.6

8

kΩ

 

VOH

High Output Level

Vcc - 1.0

–

–

V

IOH = 10 mA, Vcc = 4.75 to 5.25V.

 

 

 

 

 

 

8 total loads, 4 on even port pins

 

 

 

 

 

 

(for example, P0[2], P1[4]), 4 on

 

 

 

 

 

 

odd port pins (for example, P0[3],

 

 

 

 

 

 

P1[5]). 80 mA maximum

 

 

 

 

 

 

combined IOH budget.

VOL

Low Output Level

–

–

0.75

V

IOL = 25 mA, Vcc = 4.75 to 5.25V

 

 

 

 

 

 

8 total loads, 4 on even port pins

 

 

 

 

 

 

(for example, P0[2], P1[4]), 4 on

 

 

 

 

 

 

odd port pins (for example, P0[3],

 

 

 

 

 

 

P1[5]). 150 mA maximum

 

 

 

 

 

 

combined IOL budget.

VIL

Input Low Level

–

–

0.8

V

4.75 to 5.25.

VIH

Input High Level

2.1

–

 

V

4.75 to 5.25.

VH

Input Hysterisis

–

60

–

mV

 

IIL

Input Leakage (Absolute Value)

–

1

–

nA

Gross tested to 1 μA.

CIN

Capacitive Load on Pins as Input

–

3.5

10

pF

Pin dependent. Temp = 25oC.

COUT

Capacitive Load on Pins as Output

–

3.5

10

pF

Pin dependent. Temp = 25oC.

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram ENW PinoutsGpio ENA1 NVWNVA1 NVA2NvSRAM Operation PSoC NV Functional OverviewPSoC NV Core NvSRAM Data MemoryAdditional System Resources Programmable Digital SystemProgrammable Analog System Esigner Development ToolsPSoC Designer Software Subsystems User Module and Source Code Development Flows Designing with User ModulesHardware Tools Samples per second Cypress nvSRAM user ModuleParts per million Microhenry Picosecond MicrosecondESD Operating Temperature3V Operation Absolute Maximum RatingsDC Electrical Characteristics Psrroa CmrroaPsrr OB Resistor Unit Value Continuous Time DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Agnd = BandGap1 Agnd = 1.6 x BandGap1PORLEV10 = 00b Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00b Ppor HysteresisDuring Programming or Verify Down resistor Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify Driving internal pullDC24M AC Electrical CharacteristicsLow Voltage Trigger Level Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Store Cycle Duration 12.5Bwoa Bwob CrcprsSpim SpisData Hold Time Data Setup Time Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Setup Time for a Repeated Start Condition5V Operation Input Low Level 75 to Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Combined IOH budgetAverage Input Offset Voltage Drift Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Low power comparator LPC reference voltage range VccPsrrob VM20 = 100b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 011bBlock Output Low Voltage During Programming orVerify Internal Main Oscillator Frequency for 6 MHz Using factory trim valuesMHz Trimmed for 5V operation See onTFallF MHz Normal Strong Mode TRiseFGpio Operating Frequency Vcc = 4.75V toMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Sions Transmitter Maximum Input Clock Frequency 24.6 MHzData Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramCY8CNP102E-AXI Part Numbering NomenclatureOrdering Information CY8CNP102B-AXI81 oC/W Package DiagramsThermal Impedance TqfpGVCH/PYRS Document HistoryPyrs USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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