Cypress CY8CNP102E manual MHz Trimmed for 5V operation, Using factory trim values, See on, Cycle

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PRELIMINARY CY8CNP102B, CY8CNP102E

AC Electrical Characteristics

The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V over the Temperature range of -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

AC Chip Level Specifications

Table 33. 5V AC Chip Level Specifications (CY8CNP102E)

Symbol

Description

Min

Typ

Max

Units

Notes

F

Internal Main Oscillator Frequency for 24 MHz

23.4

24

24.6[4, 5, 6]

MHz

Trimmed for 5V operation

IMO24

 

 

 

 

 

using factory trim values.

 

 

 

 

 

 

 

 

 

 

 

 

See Figure 5 on page 9.

 

 

 

 

 

 

SLIMO Mode = 0.

FIMO6

Internal Main Oscillator Frequency for 6 MHz

5.75

6

6.35[4 , 5, 6]

MHz

Trimmed for 5V operation

 

 

 

 

 

 

using factory trim values.

 

 

 

 

 

 

See Figure 5 on page 9.

 

 

 

 

 

 

SLIMO Mode = 1.

FCPU1

CPU Frequency (5V Nominal)

0.93

24

24.6[4, 5]

MHz

 

F

Digital PSoC Block Frequency

0

48

49.2[4, 5, 7]

MHz

Refer to AC Digital Block

48M

 

 

 

 

 

Specifications on page 30.

 

 

 

 

 

 

 

 

 

 

 

 

 

F24M

Digital PSoC Block Frequency

0

24

24.6[5, 7]

MHz

 

F32K1

Internal Low Speed Oscillator Frequency

15

32

64

kHz

 

F32K2

External Crystal Oscillator

32.768

kHz

Accuracy is capacitor and

 

 

 

 

 

 

crystal dependent. 50% duty

 

 

 

 

 

 

cycle.

FPLL

PLL Frequency

23.986

MHz

A multiple (x732) of crystal

 

 

 

 

 

 

frequency.

Jitter24M2

24 MHz Period Jitter (PLL)

600

ps

 

 

 

 

 

 

 

 

TPLLSLEW

PLL Lock Time

0.5

10

ms

 

TPLLSLEWLOW

PLL Lock Time for Low Gain Setting

0.5

50

ms

 

TOS

External Crystal Oscillator Startup to 1%

250

500

ms

 

TOSACC

External Crystal Oscillator Startup to 100 ppm

300

600

ms

The crystal oscillator

 

 

 

 

 

 

frequency is within 100 ppm

 

 

 

 

 

 

of its final value by the end of

 

 

 

 

 

 

the Tosacc period. Correct

 

 

 

 

 

 

operation assumes a

 

 

 

 

 

 

properly loaded 1 uW

 

 

 

 

 

 

maximum drive level 32.768

 

 

 

 

 

 

kHz crystal.

Jitter32k

32 kHz Period Jitter

100

 

ns

 

 

 

 

 

 

 

 

TXRST

External Reset Pulse Width

10

μs

 

DC24M

24 MHz Duty Cycle

40

50

60

%

 

 

 

 

 

 

 

 

Step24M

24 MHz Trim Step Size

50

kHz

 

 

 

 

 

 

 

 

Fout48M

48 MHz Output Frequency

46.8

48.0

49.2[4,6]

MHz

Trimmed. Using factory trim

 

 

 

 

 

 

values.

Jitter24M1

24 MHz Period Jitter (IMO)

600

 

ps

 

 

 

 

 

 

 

 

FMAX

Maximum frequency of signal on row input or

12.3

MHz

 

 

row output.

 

 

 

 

 

TRAMP

Supply Ramp Time

0

μs

 

Document #: 001-43991 Rev. *D

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Contents Features OverviewLogic Block Diagram Gpio PinoutsENW NVW NVA1NVA2 ENA1PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM OperationProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per secondOperating Temperature 3V OperationAbsolute Maximum Ratings ESDDC Electrical Characteristics Cmrroa PsrroaPsrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimeVdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bSupply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistorAC Electrical Characteristics DC24MPower Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Crcprs SpimSpis BwobData Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 toInput Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100bVerify Output Low Voltage During Programming orBlock Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHzMHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l eExternal Crystal Oscillator Startup Timing Diagram L e c tPart Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXIPackage Diagrams Thermal ImpedanceTqfp 81 oC/WPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB