Cypress CY8CNP102B, CY8CNP102E manual Document History, Gvch/Pyrs

Page 37

PRELIMINARY CY8CNP102B, CY8CNP102E

Document History Page

Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV)

Document Number: 001-43991

REV.

ECN

Orig. of Change

Submission

Description of Change

Date

 

 

 

 

 

 

 

 

 

**

1941108

vsutmp8/AESA

See ECN

New Data Sheet

 

 

 

 

 

*A

2378513

PYRS

See ECN

Move to external web

 

 

 

 

 

*B

2512803

GVCH/PYRS

06/05/2008

Features: Added total no. of GPIO information in Programmable Pin

 

 

 

 

configurations

 

 

 

 

Changed Pin no.14 from P3_7 to NC in the Pin diagram

 

 

 

 

Table 1: Updated Pin definitions

 

 

 

 

Table 5: Changed Typ and max value of IDD from 25 mA and 29mA to 36 mA

 

 

 

 

and 40 mA resp.

 

 

 

 

Table 5: Changed Typ and max value of IDDP from 15 mA and 16 mA to

 

 

 

 

27 mA and 28 mA respectively.

 

 

 

 

Table 5: Changed Min and Max value of VCAP from 56 uF and 100 uF to

 

 

 

 

61 uF and 82 uF resp.

 

 

 

 

Table 6: Changed VIH min value from 2.1 mV to 1.6 mV

 

 

 

 

Added Table 12: DC POR,SMP, and LVD specifications

 

 

 

 

Table 13: Changed IDDP naming convention to IDDPV

 

 

 

 

Table 14: Updated note references

 

 

 

 

Table 17: Updated Timer, Counter, deadband and CRCPS (PRS mode)

 

 

 

 

values

 

 

 

 

Table 23: Changed Typ and max value of IDD from 28 mA and 34 mA to

 

 

 

 

39 mA and 45 mA resp.

 

 

 

 

Table 23: Changed Typ and max value of IDDP from 15 mA and 16 mA to

 

 

 

 

27 mA and 28 mA resp.

 

 

 

 

Table 23: Changed Min and Max value of VCAP from 56 uF and 100 uF to

 

 

 

 

61 uF and 82 uF resp.

 

 

 

 

Added Table 30: DC POR,SMP, and LVD specifications

 

 

 

 

Table 31: Changed IDDP naming convention to IDDPV

 

 

 

 

table 32: Updated note references

 

 

 

 

Updated Figure 14: Definition for Timing for Fast/Standard Mode on the I2C

 

 

 

 

bus

 

 

 

 

Updated part Numbering Nomenclature

 

 

 

 

Updated Thermal Impedance table

 

 

 

 

Updated data sheet template

 

 

 

 

 

*C

2571208

GVCH/PYRS

09/23/08

Changed Title from nvPSoC to PSoC NV

 

 

 

 

Updated “Features”

 

 

 

 

 

*D

2594976

GVCH/PYRS

10/22/08

Added M8C processor speeds for 3.3V and 5V operation in “Features”

 

 

 

 

Updated Logic block diagram

 

 

 

 

Changed total GPIOs from 27 to 33

 

 

 

 

Changed pin number 53 name from P1_4 to P1_6

 

 

 

 

Changed pin definition of pin 79 and 99

 

 

 

 

Table 5: Changed ISB from 3 mA to 5 mA

 

 

 

 

Updated Table 12

 

 

 

 

Table 24: Changed ISB from 3 mA to 5 mA

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram Gpio PinoutsENW NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bVerify Output Low Voltage During Programming orBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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