Cypress CY8CNP102E Supply Current During Programming or Verify, Driving internal pull, Per block

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PRELIMINARY CY8CNP102B, CY8CNP102E

DC Programming Specifications

Table 13. 3.3V DC Programming Specifications (CY8CNP102B)

Symbol	Description	Min	Typ	Max	Units	Notes
IDDPV	Supply Current During Programming or Verify	–	10	30	mA
VILP	Input Low Voltage During Programming or Verify	–	–	0.8	V
VIHP	Input High Voltage During Programming or Verify	2.2	–	–	V
IILP	Input Current when Applying Vilp to P1[0] or P1[1]	–	–	0.2	mA	Driving internal pull
	During Programming or Verify					down resistor.
IIHP	Input Current when Applying Vihp to P1[0] or P1[1]	–	–	1.5	mA	Driving internal pull
	During Programming or Verify					down resistor.
VOLV	Output Low Voltage During Programming or Verify	–	–	Vss + 0.75	V
VOHV	Output High Voltage During Programming or Verify	Vcc - 1.0	–	Vcc	V
FlashENPB	Flash Endurance (per block)	50,000	–	–	–	Erase/write cycles
						per block.
FlashENT	Flash Endurance (total)[3]	1,800,000	–	–	–	Erase/write cycles.
FlashDR	Flash Data Retention	10	–	–	Years

Note

3.A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single lock ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (Flash Temp) and feed the result to the temperature argument before timing. Refer to the Flash APIs Application Note AN2015 at http//www.cypress.com under Application Notes for more information.

Document #: 001-43991 Rev. *D

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Contents Features OverviewLogic Block Diagram Gpio PinoutsENW NVW NVA1NVA2 ENA1PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM OperationProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per secondOperating Temperature 3V OperationAbsolute Maximum Ratings ESDDC Electrical Characteristics Cmrroa PsrroaPsrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimeVdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bSupply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistorAC Electrical Characteristics DC24MPower Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Crcprs SpimSpis BwobData Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 toInput Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100bVerify Output Low Voltage During Programming orBlock Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHzMHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l eExternal Crystal Oscillator Startup Timing Diagram L e c tPart Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXIPackage Diagrams Thermal ImpedanceTqfp 81 oC/WPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB