Cypress CY8CNP102B, CY8CNP102E manual Psrrob

Page 25

PRELIMINARY CY8CNP102B, CY8CNP102E

DC Analog Output Buffer Specifications

Table 28. 5V DC Analog Output Buffer Specifications (CY8CNP102E)

Symbol

Description

Min

Typ

Max

Units

VOSOB

Input Offset Voltage (Absolute Value)

–

3

12

mV

TCVOSOB

Average Input Offset Voltage Drift

–

+6

–

μV/°C

VCMOB

Common-Mode Input Voltage Range

0.5

–

Vcc - 1.0

V

ROUTOB

Output Resistance

 

 

 

 

 

Power = Low

–

–

1

Ω

 

Power = High

–

–

1

Ω

 

 

 

 

 

 

VOHIGHOB

High Output Voltage Swing (Load = 32 ohms to Vcc/2)

 

 

 

 

 

Power = Low

0.5 x Vcc + 1.3

–

–

V

 

Power = High

0.5 x Vcc + 1.3

–

–

V

 

 

 

 

 

 

VOLOWOB

Low Output Voltage Swing (Load = 32 ohms to Vcc/2)

 

 

 

 

 

Power = Low

–

–

0.5 x Vcc - 1.3

V

 

Power = High

–

–

0.5 x Vcc - 1.3

V

 

 

 

 

 

 

ISOB

Supply Current Including Bias Cell (No Load)

 

 

 

 

 

Power = Low

–

1.1

2

mA

 

Power = High

–

2.6

5

mA

 

 

 

 

 

 

PSRROB

Supply Voltage Rejection Ratio

40

64

–

dB

DC Analog Reference Specifications

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Table 29. 5V DC Analog Reference Specifications (CY8CNP102E)

Symbol

Description

Min

Typ

Max

Units

VBG5

Bandgap Voltage Reference 5V

1.28

1.30

1.32

V

–

AGND = Vcc/2[1]

Vcc/2 - 0.02

Vcc/2

Vcc/2 + 0.02

V

–

AGND = 2 x BandGap[1]

2.52

2.60

2.72

V

–

AGND = P2[4] (P2[4] = Vcc/2)[1]

P2[4] - 0.013

P2[4]

P2[4] + 0.013

V

–

AGND = BandGap[1]

1.27

1.3

1.34

V

–

AGND = 1.6 x BandGap[1]

2.03

2.08

2.13

V

–

AGND Block to Block Variation (AGND = Vcc/2)[1]

-0.034

0.000

0.034

V

–

RefHi = Vcc/2 + BandGap

Vcc/2 + 1.21

Vcc/2 + 1.3

Vcc/2 + 1.382

V

 

 

 

 

 

 

–

RefHi = 3 x BandGap

3.75

3.9

4.05

V

 

 

 

 

 

 

–

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

P2[6] + 2.478

P2[6] + 2.6

P2[6] + 2.722

V

 

 

 

 

 

 

–

RefHi = P2[4] + BandGap (P2[4] = Vcc/2)

P2[4] + 1.218

P2[4] + 1.3

P2[4] + 1.382

V

 

 

 

 

 

 

–

RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V)

P2[4] + P2[6] - 0.058

P2[4] + P2[6]

P2[4] + P2[6] + 0.058

V

 

 

 

 

 

 

–

RefHi = 2 x BandGap

2.50

2.60

2.70

V

 

 

 

 

 

 

–

RefHi = 3.2 x BandGap

4.02

4.16

4.29

V

 

 

 

 

 

 

–

RefLo = Vcc/2 – BandGap

Vcc/2 - 1.369

Vcc/2 - 1.30

Vcc/2 - 1.231

V

 

 

 

 

 

 

–

RefLo = BandGap

1.20

1.30

1.40

V

 

 

 

 

 

 

–

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

2.489 - P2[6]

2.6 - P2[6]

2.711 - P2[6]

V

 

 

 

 

 

 

–

RefLo = P2[4] – BandGap (P2[4] = Vcc/2)

P2[4] - 1.368

P2[4] - 1.30

P2[4] - 1.232

V

 

 

 

 

 

 

–

RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V)

P2[4] - P2[6] - 0.042

P2[4] - P2[6]

P2[4] - P2[6] + 0.042

V

 

 

 

 

 

 

Document #: 001-43991 Rev. *D

 

 

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Contents Overview FeaturesLogic Block Diagram Gpio PinoutsENW NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationProgrammable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bVerify Output Low Voltage During Programming orBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WPyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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