Cypress CY8CNP102B manual Vdd Value for Ppor Trip positive ramp, PORLEV10 = 00b Ppor Hysteresis

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PRELIMINARY CY8CNP102B, CY8CNP102E

DC POR, SMP, and LVD Specifications

Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B)

Symbol

Description

Min

Typ

Max

Units

 

Vdd Value for PPOR Trip (positive ramp)

 

 

 

 

 

 

 

 

 

 

VPPOR0R

PORLEV[1:0] = 00b

 

2.91

 

V

 

Vdd Value for PPOR Trip (negative ramp)

 

 

 

 

 

 

 

 

 

 

VPPOR0

PORLEV[1:0] = 00b

 

2.82

 

V

 

PPOR Hysteresis

 

 

 

 

 

 

 

 

 

 

VPH0

PORLEV[1:0] = 00b

 

92

 

mV

VPH1

PORLEV[1:0] = 01b

 

0

 

mV

VPH2

PORLEV[1:0] = 10b

 

0

 

mV

 

Vdd Value for LVD Trip

 

 

 

 

 

 

 

 

 

 

VLVD0

VM[2:0] = 000b

2.86

2.92

2.98[2]

V

VLVD1

VM[2:0] = 001b

2.96

3.02

3.08

V

VLVD2

VM[2:0] = 010b

3.07

3.13

3.20

V

 

Vdd Value for SMP Trip

 

 

 

 

 

 

 

 

 

 

VPUMP0

VM[2:0] = 000b

2.96

3.02

3.08

V

VPUMP1

VM[2:0] = 001b

3.03

3.10

3.16

V

VPUMP2

VM[2:0] = 010b

3.18

3.25

3.32

V

Note

2. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

Document #: 001-43991 Rev. *D

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Contents Overview FeaturesLogic Block Diagram Pinouts GpioENW ENA1 NVWNVA1 NVA2NvSRAM Operation PSoC NV Functional OverviewPSoC NV Core NvSRAM Data MemoryProgrammable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Samples per second Cypress nvSRAM user ModuleParts per million Microhenry Picosecond MicrosecondESD Operating Temperature3V Operation Absolute Maximum RatingsDC Electrical Characteristics Psrroa CmrroaPsrr OB Resistor Unit Value Continuous Time DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Agnd = BandGap1 Agnd = 1.6 x BandGap1PORLEV10 = 00b Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00b Ppor HysteresisDuring Programming or Verify Down resistor Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify Driving internal pullDC24M AC Electrical CharacteristicsLow Voltage Trigger Level Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Store Cycle Duration 12.5Bwoa Bwob CrcprsSpim SpisData Hold Time Data Setup Time Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Setup Time for a Repeated Start Condition5V Operation Input Low Level 75 to Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Combined IOH budgetAverage Input Offset Voltage Drift Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Low power comparator LPC reference voltage range VccPsrrob VM20 = 100b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 011bOutput Low Voltage During Programming or VerifyBlock Internal Main Oscillator Frequency for 6 MHz Using factory trim valuesMHz Trimmed for 5V operation See onTFallF MHz Normal Strong Mode TRiseFGpio Operating Frequency Vcc = 4.75V toMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Sions Transmitter Maximum Input Clock Frequency 24.6 MHzData Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramCY8CNP102E-AXI Part Numbering NomenclatureOrdering Information CY8CNP102B-AXI81 oC/W Package DiagramsThermal Impedance TqfpDocument History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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