Cypress CY8CNP102B, CY8CNP102E manual Bwoa

PRELIMINARY CY8CNP102B, CY8CNP102E

AC Operational Amplifier Specifications

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B)

Symbol	Description	Min	Typ	Max	Units	Notes
TROA	Rising Settling Time to 0.1% of a 1V Step					Power = High and
	(10 pF load, Unity Gain)					Opamp Bias = High is
	Power = Low, Opamp Bias = Low	–	–	3.92	μs	not supported at
						3.3V.
	Power = Medium, Opamp Bias = High	–	–	0.72	μs
TSOA	Falling Settling Time to 0.1% of a 1V Step
	(10 pF load, Unity Gain)
	Power = Low, Opamp Bias = Low	–	–	5.41	μs
	Power = Medium, Opamp Bias = High	–	–	0.72	μs
SRROA	Rising Slew Rate (20% to 80%) of a 1V Step
	(10 pF load, Unity Gain)
	Power = Low, Opamp Bias = Low	0.31	–	–	V/μs
	Power = Medium, Opamp Bias = High	2.7	–	–	V/μs
SRFOA	Falling Slew Rate (20% to 80%) of a 1V Step
	(10 pF load, Unity Gain)
	Power = Low, Opamp Bias = Low	0.24	–	–	V/μs
	Power = Medium, Opamp Bias = High	1.8	–	–	V/μs
BWOA	Gain Bandwidth Product
	Power = Low, Opamp Bias = Low	0.67	–	–	MHz
	Power = Medium, Opamp Bias = High	2.8	–	–	MHz
ENOA	Noise at 1 kHz	–	100	–	nV/rt-Hz
	(Power = Medium, Opamp Bias = High)
AC Digital Block Specifications
Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B)
Function	Description	Min	Typ	Max	Units	Notes
All Functions	Maximum Block Clocking Frequency			24.6	MHz	3.0V ≤ Vcc ≤ 3.6V
Timer	Capture Pulse Width	50[8]	–	–	ns
	Maximum Frequency, No Capture	–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V.
	Maximum Frequency, With Capture	–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V.
Counter	Enable Pulse Width	50[8]	–	–	ns
	Maximum Frequency, No Enable Input	–	–	24.6	MHz	3.0V ≤ Vcc ≤3.6V.
	Maximum Frequency, Enable Input	–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V.
Dead Band	Kill Pulse Width:
	Asynchronous Restart Mode	20	–	–	ns
	Synchronous Restart Mode	50[8]	–	–	ns
	Disable Mode	50[8]	–	–	ns
	Maximum Frequency	–	–	24.6	MHz	3.0V ≤ Vcc ≤ 3.6V

Note

8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document #: 001-43991 Rev. *D Page 19 of 38

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