Cypress CY8CNP102B, CY8CNP102E Cypress nvSRAM user Module, Parts per million, Samples per second

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PRELIMINARY CY8CNP102B, CY8CNP102E

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. The Debugger capabilities rival those of systems costing much more. In addition to traditional single step, run to breakpoint, and watch variable features, the Debugger provides a large trace buffer enabling you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.

Cypress nvSRAM user Module

The nvSRAM user module is integrated with the PSoC Designer tool and contains APIs that facilitate nvSRAM access and control. The user module provides high level access to the nvSRAM without user developed code. The user module API also provides the ability to read and write arbitrary data struc- tures to or from the nvSRAM, and initiate nvSRAM Store or Recall operations.

Electrical Specifications

This section lists the PSoC NV device DC and AC electrical specifications. Specifications are valid for -40oC TA 85oC, and TJ 100oC, except where noted.

Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator (IMO) using SLIMO mode.

Figure 4. Voltage versus CPU Frequency

Figure 5. IMO Frequency Trim Options

5.25

 

 

 

Operating Region

 

 

(CY8CNP102E)

 

4.75

 

 

 

R

 

 

e

 

Vdd

g

 

i

 

o

 

n

 

3.60

 

 

Voltage

Operating Region

 

 

(CY8CNP102B)

 

3.00

 

 

93 kHz

12 MHz

24 MHz

CPU Frequency

5.25

0

 

 

 

 

SLIMO

 

SLIMO

 

 

=

 

Mode=0

 

Mode=1

 

4.75

SLIMOMode

 

 

Vdd Voltage

 

 

3.60

SLIMO

 

SLIMO

 

 

3.00

Mode=1

 

Mode=0

 

 

 

93 kHz

6 MHz

12 MHz

24 MHz

IMO Frequency

The following table lists the units of measure that are used in this data sheet.

Table 2. Units of Measure

Symbol

Unit of Measure

Symbol

Unit of Measure

oC

degree Celsius

μW

microwatts

dB

decibels

mA

milli-ampere

 

 

 

 

fF

femto farad

ms

milli-second

 

 

 

 

Hz

hertz

mV

milli-volts

 

 

 

 

KB

1024 bytes

nA

nanoampere

 

 

 

 

Kbit

1024 bits

ns

nanosecond

 

 

 

 

kHz

kilohertz

nV

nanovolts

 

 

 

 

kΩ

kilohm

Ω

ohm

 

 

 

 

MHz

megahertz

pA

picoampere

 

 

 

 

MΩ

megaohm

pF

picofarad

 

 

 

 

μA

microampere

pp

peak-to-peak

 

 

 

 

μF

microfarad

ppm

parts per million

 

 

 

 

μH

microhenry

ps

picosecond

 

 

 

 

μs

microsecond

sps

samples per second

 

 

 

 

μV

microvolts

σ

sigma: one standard deviation

 

 

 

 

μVrms

microvolts root-mean-square

V

volts

 

 

 

 

Document #: 001-43991 Rev. *D

 

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Contents Overview FeaturesLogic Block Diagram Pinouts GpioENW NVA1 NVWNVA2 ENA1PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM OperationProgrammable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second3V Operation Operating TemperatureAbsolute Maximum Ratings ESDDC Electrical Characteristics Psrroa CmrroaPsrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous TimePORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00bInput Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistorDC24M AC Electrical CharacteristicsGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger LevelBwoa Spim CrcprsSpis BwobData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 toGross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage DriftPsrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100bOutput Low Voltage During Programming or VerifyBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHzGpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallFMaximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching WaveformsL e c t External Crystal Oscillator Startup Timing DiagramOrdering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXIThermal Impedance Package DiagramsTqfp 81 oC/WDocument History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB