Xilinx SP605 manual U1 Fpga

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Detailed Description

Table 1-5:	DDR3 Component Memory Connections (Cont’d)

U1 FPGA		Schematic Net Name	Memory U42
U1 FPGA
Pin
			Pin Number		Pin Name



T1		MEM1_DQ9	C3		DQ9

U3		MEM1_DQ10	A2		DQ13

U1		MEM1_DQ11	D7		DQ8

W3		MEM1_DQ12	A3		DQ15

W1		MEM1_DQ13	C8		DQ10

Y2		MEM1_DQ14	B8		DQ14

Y1		MEM1_DQ15	A7		DQ12


H2		MEM1_WE_B	L3		WE_B

M5		MEM1_RAS_B	J3		RAS_B

M4		MEM1_CAS_B	K3		CAS_B

L6		MEM1_ODT	K1		ODT

K4		MEM1_CLK_P	J7		CLK_P

K3		MEM1_CLK_N	K7		CLK_N

F2		MEM1_CKE	K9		CKE

N3		MEM1_LDQS_P	F3		LDQS_P

N1		MEM1_LDQS_N	G3		LDQS_N

V2		MEM1_UDQS_P	C7		UDQS_P

V1		MEM1_UDQS_N	B7		UDQS_N

N4		MEM1_LDM	E7		LDM

P3		MEM1_UDM	D3		UDM

E3		MEM1_RESET_B	T2		RESET_B

References

See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]

Also, see the Spartan-6 FPGA Memory Controller User Guide. [Ref 3]

SP605 Hardware User Guide

www.xilinx.com

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UG526 (v1.1.1) February 1, 2010

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Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0PHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsControlled LED User I/OUser LEDs 23User LED Connections U1 Fpga PinSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References