Xilinx How to Use SFP Interface with FPGA on SP605 Evaluation Board

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Chapter 1: SP605 Evaluation Board

10. SFP Module Connector

The board contains a small form-factor pluggable (SFP) connector and cage assembly that accepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FPGA. The SFP module serial ID interface is connected to the "SFP" IIC bus (see “14. IIC Bus,” page 35 for more information). The control and status signals for the SFP module are connected to jumpers and test points as described in Table 1-12. The SFP module connections are shown in Table 1-13.

Table 1-12:SFP Module Control and Status

SFP Control/Status Signal	Board Connection

	Test Point J15
SFP_TX_FAULT	High = Fault
	Low = Normal Operation

	Jumper J44
SFP_TX_DISABLE	Off = SFP Enabled
	On = SFP Disabled

	Test Point J16
SFP_MOD_DETECT	High = Module Not Present
	Low = Module Present

	Jumper J22
SFP_RT_SEL	Jumper Pins 1-2 = Full Bandwidth
	Jumper Pins 2-3 = Reduced Bandwidth

	Test Point J14
SFP_LOS	High = Loss of Receiver Signal
	Low = Normal Operation

Table 1-13:SFP Module Connections

	U1 FPGA Pin	Schematic Net Name	P2 SFP Module Connector

			Pin Number	Pin Name
			Pin Number	Pin Name

	D13	SFP_RX_P	13	RDP

	C13	SFP_RX_N	12	RDN

	B14	SFP_TX_P	18	TDP

	A14	SFP_TX_N	19	TDN

	T17	SFP_LOS	8	LOS

	Y8	SFP_TX_DISABLE_FPGA	3	TX_DISABLE

	A12	SFPCLK_QO_N(1)	U47.6(2)	-
	B12	SFPCLK_QO_P(1)	U47.7(2)	-

Notes:

1.The 125MHz SFP clock is sourced by clock driver U47.

2.Not P2 SFP module pins.

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		UG526 (v1.1.1) February 1, 2010

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Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References SFP Module Connector SfpclkqopBit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED Connections23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References