Xilinx SP605 manual USB Jtag

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Chapter 1: SP605 Evaluation Board

Table 1-8:System ACE CF Connections (Cont’d)

	U1 FPGA Pin	Schematic Net Name(1)	U17 XCCACETQ144I

			Pin Number	Pin Name
			Pin Number	Pin Name

	AA1	SYSACE_MPBRDY	39	MPBRDY

	W4	SYSACE_MPCE	42	MPCE

	AA2	SYSACE_MPIRQ	41	MPIRQ

	T6	SYSACE_MPOE	77	MPOE

	T5	SYSACE_MPWE	76	MPWE

	G17	SYSACE_CFGTDI	81	CFGTDI

	A21	FPGA_TCK	80	CFGTCK

	E18	FPGA_TDI	82	CFGTDO

	D20	FPGA_TMS	85	CFGTMS

	N19	CLK_33MHZ_SYSACE(2)	93	CLK

Notes:

1.U17 System ACE CF controller 3.3V signals as named are wired to a set of TXB0108 3.3V-to-1.5V level shifters. The nets between the 1.5V side of the level shifters and the U1 FPGA have the same names with _LS appended.

2.The System ACE CF clock is sourced from U29 32.000MHz oscillator.

References

See the System ACE CF product page for more information at http://www.xilinx.com/support/documentation/system_ace_solutions.htm.

In addition, see the System ACE CompactFlash Solution Data Sheet. [Ref 5]

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the SP605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated in Figure 1-6. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.

J4

USB Header

	FMC LPC
Buffer	TDI	TDO

J2

J19	3.3V	2.5V

System ACE CF

FPGA

TSTTDI CFGTDO TDI

TSTTDO CFGTDI TDO

U17

U1

UG526_06_092409

Figure 1-6:JTAG Chain Diagram

22	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

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Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References SFP Module Connector SfpclkqopBit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED Connections23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References