Xilinx manual SP605 Features

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Chapter 1: SP605 Evaluation Board

Related Xilinx Documents

Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools and solutions:

•ISE: www.xilinx.com/ise

•Answer Browser: www.xilinx.com/support

•Intellectual Property: www.xilinx.com/ipcenter

Detailed Description

Figure 1-2shows a board photo with numbered features corresponding to Table 1-1and the section headings in this document.

15e

15h

18

15b 15a

16d

6

12

16c

10

7a

2

5

15c

17d

17b 17a

15d

11

3

13

4

1

15g

8

7b

16a 15f

9

8	7c

16b

19b

17c

19

3, 14 (on backside)

UG526_02 _110409

Figure 1-2:SP605 Board Photo

The numbered features in Figure 1-2correlate to the features and notes listed in Table 1-1.

	Table 1-1:	SP605 Features

	Number	Feature	Notes	Schematic
	Number	Feature	Notes	Page
				Page

	1	Spartan-6 FPGA	XC6SLX45T-3FGG484 FPGA	2–7

	2	DDR3 Component Memory	Micron MT41J64M16LA-187E	9

	3	SPI Header Ext. x4	Winbond W25Q64VSFIG	18
	3	SPI Flash x4 (on backside)	Winbond W25Q64VSFIG	18
		SPI Flash x4 (on backside)

10	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

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Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References SFP Module Connector SfpclkqopBit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED Connections23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References