Xilinx manual Configuration Options, 30SP605 Fpga Configuration Modes M10 Bus Width

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Configuration Options

Configuration Options

The FPGA on the SP605 Evaluation Board can be configured by the following methods:

“3. SPI x4 Flash,” page 16

“4. Linear BPI Flash,” page 18

“5. System ACE CF and CompactFlash Connector,” page 20

“6. USB JTAG,” page 22

For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2]

Table 1-30:SP605 FPGA Configuration Modes

Configuration

M[1:0]

Bus Width

CCLK

Configuration Solution

User Guide Section

Mode

Direction

 

 

 

 

 

 

 

 

 

 

Master Serial/SPI

01

1, 2, 4(1)

Output

SPI X4 Memory U32 (J46 on), or

3. SPI x4 Flash

External SPI Header J17 (J46 off)

 

 

 

 

 

 

 

 

 

 

 

Master

00

8, 16

Output

Linear Flash Memory U25 (BPI)

4. Linear BPI Flash

SelectMAP/BPI(2)

 

 

 

 

 

JTAG(3)

xx

1

Input

Xilinx Platform Cable USB

6. USB JTAG

(TCK)

plugged into J4

 

 

 

 

 

 

 

 

 

 

Slave SelectMAP(2)

10

8, 16

Input

System ACE CF Controller and

5. System ACE CF and

CompactFlash Card

CompactFlash Connector

 

 

 

 

 

 

 

 

 

 

Slave Serial(4)

11

1

Input

Not Supported

Notes:

1.Utilizing dual and quad SPI modes.

2.Parallel configuration mode bus is auto-detected by the configuration logic.

3.Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the mode pin settings.

4.Default setting due to internal pull-up termination on Mode pins.

With the mode switch SW1 set to 01, the SP605 will attempt to boot or load a bitstream from either the SPI X4 Flash device U32 or a user supplied SPI Flash memory mezzanine card installed on the SPI programming header J17, depending on the SPI select jumper J46 configuration, as shown in Table 1-30. With the mode set to 00, the SP605 will attempt to boot or load a bitstream from Linear Flash device U25 (BPI).

With the mode switch SW1 set to 10, if a CompactFlash (CF) card is installed in the CF socket U37, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1. With no CF card present, the SP605 can be configured via the onboard JTAG controller and USB download cable as described in “6. USB JTAG,” page 22.

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0PHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsControlled LED User I/OUser LEDs 23User LED Connections U1 Fpga PinSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References