Xilinx SP605 manual User I/O, User LEDs, 23User LED Connections U1 Fpga Pin, Controlled LED

Page 41

Detailed Description

16. User I/O

The SP605 provides the following user and general purpose I/O capabilities:

User LEDs

User Pushbutton Switches

User DIP Switch

User SIP Header

User SMA GPIO

User LEDs

The SP605 provides four active-High green LEDs as described in Figure 1-15and

Table 1-23.

GPIO LED 3

GPIO LED 2

 

 

 

 

 

 

 

 

 

 

GPIO LED 1

 

 

 

 

 

 

 

 

 

 

GPIO LED 0

 

 

 

 

 

 

 

 

 

 

 

2

 

 

2

 

 

2

 

 

2

LED-

DS3

LED-

 

DS4

LED-

 

DS5

LED-

 

DS6

GRN-S

1

GRN-S

 

1

GRN-S

 

1

GRN-S

 

1

MT

 

MT

 

 

MT

 

 

MT

 

 

1

R74

 

1

R73

 

1

R72

 

1

R71

 

 

 

 

 

 

 

 

27.4

 

 

27.4

 

 

27.4

 

 

27.4

2

1%

 

2

1%

 

2

1%

 

2

1%

1/16W

 

1/16W

 

1/16W

 

1/16W

 

 

 

 

 

 

 

UG526_15_092409

Figure 1-15: User LEDs

Table 1-23:User LED Connections

U1 FPGA Pin

Schematic Net Name

Controlled LED

 

 

 

D17

GPIO_LED_0

DS3

 

 

 

AB4

GPIO_LED_1

DS4

 

 

 

D21

GPIO_LED_2

DS5

 

 

 

W15

GPIO_LED_3

DS6

 

 

 

SP605 Hardware User Guide

www.xilinx.com

41

UG526 (v1.1.1) February 1, 2010

Image 41
Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d Voltage Rails MB DDR3 Component MemoryDetailed Description 2I/O Voltage Rail of Fpga Banks5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References Sfpclkqop SFP Module Connector11 /100/1000 Tri-Speed Ethernet PHY 14PHY Configuration PinsBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsUser LEDs User I/O23User LED Connections U1 Fpga Pin Controlled LEDSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References