Xilinx SP605 manual Onboard Power Regulation, Power Management

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Power Management

Onboard Power Regulation

Figure 1-25shows the SP605 onboard power supply architecture. The SP605 uses Texas Instruments power controllers for primary core power control and monitoring.

Power Supply

12V

PWR

Jack

J18 or J27

Linear Regulator

U5

5.0V@1.5A max TL1963AKTTR

Op Amps

Linear Regulator

U49

3.0V@500mA max LT1763CS8

SPI x4 Memory

		Power Controller 1			U26
		UCD9240PFC

		Switching Module			U18			FPGA
		VCCINT 1.2V@10A max
		VCCINT 1.2V@10A max
		PTD08A010W

		Switching Module			U20			FPGA
		VCCAUX 2.5V@10A max
		VCCAUX 2.5V@10A max
		PTD08A010W

		Switching Module			U19			FPGA
		VCC 2.5V@10A max
		VCC 2.5V@10A max
		PTD08A010W


				Linear Regulator			U44	Linear FLash Memory
				1.8V@500mA max
				1.8V@500mA max
				TL1963A-18DCQR

	Power Controller 2	U27
	UCD9240PFC
	Switching Module	U22
	3.3V@10A max
	PTD08A010W


	Switching Module	U21
	1.5V@10A max
	PTD08A010W

System Power

DDR3 Memory

1.5V

10K

0.75Vref

10K 3.3V

Linear Regulator

U51

MGT AVCC 1.2V@3A max TPS74401

Sink/Source Regulator U11

0.75VTT/VREF@3A max TPS51200DRCT

MGTs

DDR3 Memory Terminations

UG526_25_100509

Figure 1-25:Onboard Power Regulators

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

Image 53

Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d Voltage Rails MB DDR3 Component MemoryDetailed Description 2I/O Voltage Rail of Fpga Banks5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References Sfpclkqop SFP Module Connector11 /100/1000 Tri-Speed Ethernet PHY 14PHY Configuration PinsBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsUser LEDs User I/O23User LED Connections U1 Fpga Pin Controlled LEDSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References