Xilinx SP605 manual User SIP Header, U1 Fpga Pin

Page 44

Chapter 1: SP605 Evaluation Board

User SIP Header

The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access. Four pins of J55 are wired to the FPGA through 200 ohm series resistors and a level shifter, and the remaining two J55 pins are wired to 3.3V and GND. The J55 header is described in Figure 1-18and Table 1-26.

Note: This header is not installed on the SP605 as built.

VCC1V5_FPGAVCC3V3

 

 

 

 

 

 

 

 

 

 

 

 

U52

 

U1 FPGA Pin

 

 

 

 

2

 

VCCA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G7

 

 

 

GPIO_HEADER_0_LS

1

 

 

 

 

 

A1

 

 

 

 

 

 

 

GPIO_HEADER_1_LS

3

 

 

H6

 

 

 

 

A2

 

 

 

 

 

 

 

GPIO_HEADER_2_LS

4

 

 

D1

 

 

 

 

 

A3

 

R7

 

 

 

 

GPIO_HEADER_3_LS

5

 

A4

 

 

 

 

 

 

 

 

NC

6

 

A5

 

 

 

 

 

 

 

 

NC

7

 

A6

 

 

 

 

 

 

 

 

NC

8

 

A7

 

 

 

 

 

 

 

 

NC

9

 

A8

 

 

 

 

 

 

 

 

 

 

10

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXB0108

 

 

 

 

 

 

 

 

 

 

 

 

C385

X5R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCB 1920

B1

B2 18

B3 17

B4 16

B5 15

B6 14

B7 13

B8 12

GND 11

10V

0.1UF

 

 

2

 

GPIO_HEADER_0 GPIO_HEADER_1 GPIO_HEADER_2 GPIO_HEADER_3

NC

NC

NC

NC

1C384

X5R

210V

0.1UF

GPIO_HEADER_0

R280

200

5%

1/16W

R281

 

1/16W

1

2

200 5%

GPIO_HEADER_1

R282

200

5%

1/16W

1

2

GPIO_HEADER_2

1

2

R283

200 5%

1/16W

GPIO_HEADER_3

 

 

 

 

1

 

2

 

 

 

 

 

 

HDR_1x6

J55

1

2

3

4

5

6

DNP

VCC3V3

UG526_18 _092409

Figure 1-18:User SIP Header J55

Table 1-26:User SIP Header Connections

U1 FPGA Pin

Schematic Net Name

GPIO Header Pin

 

 

 

G7

GPIO_HEADER_0

J55.1

 

 

 

H6

GPIO_HEADER_1

J55.2

 

 

 

D1

GPIO_HEADER_2

J55.3

 

 

 

R7

GPIO_HEADER_3

J55.4

 

 

 

GND

J55.5

 

 

 

VCC3V3

J55.6

 

 

 

Notes:

1.Each GPIO_HEADER_n signal is sourced from the FPGA as <netname>_LS to a level shifter, then to the J55 header.

2.Each GPIO_HEADER_n net has a 200 ohm series resistor between the level shifter and its respective header pin.

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SP605 Hardware User Guide

 

 

UG526 (v1.1.1) February 1, 2010

Image 44
Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d MB DDR3 Component Memory Voltage RailsDetailed Description 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References SFP Module Connector Sfpclkqop14PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED ConnectionsUser I/O User LEDs23User LED Connections U1 Fpga Pin Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References