Xilinx SP605 manual Vita 57.1 FMC LPC Connector

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Chapter 1: SP605 Evaluation Board

18. VITA 57.1 FMC LPC Connector

The SP605 implements the Low Pin Count (LPC, J2) connector option of the VITA 57.1.1 FMC specification.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC LPC connector provides connectivity for:

•68 single-ended or 34 differential user defined signals

•1 MGT

•1 MGT clock

•2 differential clocks

•61 ground, 10 power connections

Of the above signal and clock connectivity capability, the SP605 implements the full set:

•34 differential user-defined pairs

♦ 34 LA pairs

•1 MGT

•1 MGT clock

•2 differential clocks

Note: The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V (non- adjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

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		UG526 (v1.1.1) February 1, 2010

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Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References SFP Module Connector SfpclkqopBit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED Connections23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References