Xilinx SP605 manual 11 /100/1000 Tri-Speed Ethernet PHY, 14PHY Configuration Pins, Bit2 Bit1 Bit0

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Detailed Description

11. 10/100/1000 Tri-Speed Ethernet PHY

The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-14. These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-14:PHY Configuration Pins

	Pin	Connection on	Bit[2]	Bit[1]	Bit[0]
	Pin	Board	Definition and Value	Definition and Value	Definition and Value
		Board	Definition and Value	Definition and Value	Definition and Value

	CFG2	VCC 2.5V	ANEG[3] = 1	ANEG[2] = 1	ANEG[1] = 1
	CFG3	VCC 2.5V	ANEG[0] = 1	ENA_XC = 1	DIS_125 = 1
	CFG4	VCC 2.5V	HWCFG_MD[2] = 1	HWCFG_MD[1] = 1	HWCFG_MD[0] = 1
	CFG5	VCC 2.5V	DIS_FC = 1	DIS_SLEEP = 1	HWCFG_MD[3] = 1
	CFG6	PHY_LED_RX	SEL_BDT = 0	INT_POL = 1	75/50 OHM = 0

Table 1-15shows the connections and pin numbers for the PHY.

Table 1-15:Ethernet PHY Connections

	U1 FPGA Pin	Schematic Net Name	U46 M88E111

			Pin Number	Pin Name
			Pin Number	Pin Name

	V20	PHY_MDIO	33	MDIO

	R19	PHY_MDC	35	MDC

	J20	PHY_INT	32	INT_B

	J22	PHY_RESET	36	RESET_B

	N15	PHY_CRS	115	CRS

	M16	PHY_COL	114	COL

	P20	PHY_RXCLK	7	RXCLK

	U20	PHY_RXER	8	RXER

	T22	PHY_RXCTL_RXDV	4	RXDV

	P19	PHY_RXD0	3	RXD0

	Y22	PHY_RXD1	128	RXD1

	Y21	PHY_RXD2	126	RXD2

	W22	PHY_RXD3	125	RXD3

	W20	PHY_RXD4	124	RXD4

	V22	PHY_RXD5	123	RXD5

	V21	PHY_RXD6	121	RXD6

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0PHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsControlled LED User I/OUser LEDs 23User LED Connections U1 Fpga PinSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References