Xilinx SP605 manual NET MEM1LDQSN LOC

Page 64

Appendix C: SP605 Master UCF

NET "MEM1_LDQS_N"

LOC

=

"N1";

## G3

on U42

NET "MEM1_LDQS_P"

LOC

=

"N3";

## F3

on U42

NET "MEM1_ODT"

LOC

=

"L6";

## K1

on U42

NET "MEM1_RAS_B"

LOC

=

"M5";

## J3

on U42

NET "MEM1_RESET_B"

LOC

=

"E3";

## T2

on U42

NET "MEM1_UDM"

LOC

=

"P3";

## D3

on U42

NET "MEM1_UDQS_N"

LOC

=

"V1";

## B7

on U42

NET "MEM1_UDQS_P"

LOC

=

"V2";

## C7

on U42

NET "MEM1_WE_B"

LOC

=

"H2";

## L3

on U42

##

 

 

 

 

 

NET "PCIE_250M_N"

LOC

=

"B10";

## 1

on series C301 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_N -> 17 on U48

NET "PCIE_250M_P"

LOC

=

"A10";

## 1

on series C300 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_P -> 18 on U48

NET "PCIE_PERST_B_LS"

LOC = "J7";

## 6 on U52 (level shifter, U52.20 <-> PCIE_PERST_B <-> series R55 15 ohm <-> A11 on P4

NET "PCIE_RX0_N"

LOC =

"C7";

## B15

on P4

NET "PCIE_RX0_P"

LOC =

"D7";

## B14

on P4

NET "PCIE_TX0_N"

LOC =

"A6";

## 2

on series C26 0.1uF, C26 pin 1 -> PCIE_TX0_C_N -> A17 of P4

NET "PCIE_TX0_P"

LOC =

"B6";

## 2

on series C27 0.1uF, C26 pin 1 -> PCIE_TX0_C_P -> A16 of P4

##

 

 

 

 

 

NET "PHY_COL"

LOC =

"M16";

## 114

on U46

NET "PHY_CRS"

LOC =

"N15";

## 115

on U46

NET "PHY_INT"

LOC =

"J20";

## 32

on U46

NET "PHY_MDC"

LOC =

"R19";

## 35

on U46

NET "PHY_MDIO"

LOC =

"V20";

## 33

on U46

NET "PHY_RESET"

LOC =

"J22";

## 36

on U46

NET "PHY_RXCLK"

LOC =

"P20";

## 7

on U46

NET "PHY_RXCTL_RXDV"

LOC =

"T22";

## 4

on U46

NET "PHY_RXD0"

LOC =

"P19";

## 3

on U46

NET "PHY_RXD1"

LOC =

"Y22";

## 128

on U46

NET "PHY_RXD2"

LOC =

"Y21";

## 126

on U46

NET "PHY_RXD3"

LOC =

"W22";

## 125

on U46

NET "PHY_RXD4"

LOC =

"W20";

## 124

on U46

NET "PHY_RXD5"

LOC =

"V22";

## 123

on U46

NET "PHY_RXD6"

LOC =

"V21";

## 121

on U46

NET "PHY_RXD7"

LOC =

"U22";

## 120

on U46

NET "PHY_RXER"

LOC =

"U20";

## 8

on U46

NET "PHY_TXCLK"

LOC =

"L20";

## 10

on U46

NET "PHY_TXCTL_TXEN"

LOC =

"T8";

## 16

on U46

NET "PHY_TXC_GTXCLK"

LOC =

"AB7";

## 14

on U46

NET "PHY_TXD0"

LOC =

"U10";

## 18

on U46

NET "PHY_TXD1"

LOC =

"T10";

## 19

on U46

NET "PHY_TXD2"

LOC =

"AB8";

## 20

on U46

NET "PHY_TXD3"

LOC =

"AA8";

## 24

on U46

NET "PHY_TXD4"

LOC =

"AB9";

## 25

on U46

NET "PHY_TXD5"

LOC =

"Y9";

## 26

on U46

NET "PHY_TXD6"

LOC =

"Y12";

## 28

on U46

NET "PHY_TXD7"

LOC =

"W12";

## 29

on U46

NET "PHY_TXER"

LOC =

"U8";

## 13

on U46

##

 

 

 

 

 

NET "PMBUS_ALERT"

LOC =

"D3";

## 35

on U26, 35 on U27

NET "PMBUS_CLK"

LOC =

"W10";

## 19

on U26, 19 on U27

NET "PMBUS_CTRL"

LOC =

"H16";

## 36

on U26, 36 on U27

NET "PMBUS_DATA"

LOC =

"Y10";

## 20

on U26, 20 on U27

##

 

 

 

 

 

NET "SFPCLK_QO_N"

LOC =

"B12";

## 2

on series C298 0.1uF, C298 pin 1 <- SFPCLK_QO_C_N <- 6 of U47

NET "SFPCLK_QO_P"

LOC =

"A12";

## 2

on series C299 0.1uF, C299 pin 1 <- SFPCLK_QO_C_P <- 7 of U47

NET "SFP_LOS"

LOC =

"T17";

## 8

on P2, 1 on J14

NET "SFP_RX_N"

LOC =

"C13";

## 12

on P2

NET "SFP_RX_P"

LOC =

"D13";

## 13

on P2

NET "SFP_TX_DISABLE_FPGA"

LOC =

"Y8";

## 3

on P2, 1 on J44

NET "SFP_TX_N"

LOC =

"A14";

## 19

on P2

NET "SFP_TX_P"

LOC =

"B14";

## 18

on P2

##

 

 

 

 

 

NET "SMA_REFCLK_N"

LOC =

"D11";

##

 

NET "SMA_REFCLK_P"

LOC =

"C11";

##

 

NET "SMA_RX_N"

LOC =

"C9";

##

 

NET "SMA_RX_P"

LOC =

"D9";

##

 

NET "SMA_TX_N"

LOC =

"A8";

##

 

NET "SMA_TX_P"

LOC =

"B8";

##

 

##

 

 

 

 

 

NET "SPI_CS_B"

LOC =

"AA3";

##

 

##

 

 

 

 

 

NET "SYSACE_CFGTDI"

LOC =

"G17";

##

 

NET "SYSACE_D0_LS"

LOC =

"N6";

##

 

NET "SYSACE_D1_LS"

LOC =

"N7";

##

 

NET "SYSACE_D2_LS"

LOC =

"U4";

##

 

NET "SYSACE_D3_LS"

LOC =

"T4";

##

 

NET "SYSACE_D4_LS"

LOC =

"P6";

##

 

NET "SYSACE_D5_LS"

LOC =

"P7";

##

 

NET "SYSACE_D6_LS"

LOC =

"T3";

##

 

NET "SYSACE_D7_LS"

LOC =

"R4";

##

 

NET "SYSACE_MPA00_LS"

LOC =

"V5";

##

 

NET "SYSACE_MPA01_LS"

LOC =

"V3";

##

 

NET "SYSACE_MPA02_LS"

LOC =

"P5";

##

 

NET "SYSACE_MPA03_LS"

LOC =

"P4";

##

 

NET "SYSACE_MPA04_LS"

LOC =

"H4";

##

 

NET "SYSACE_MPA05_LS"

LOC =

"G4";

##

 

NET "SYSACE_MPA06_LS"

LOC =

"D2";

##

 

NET "SYSACE_MPBRDY_LS"

LOC =

"AA1";

##

 

NET "SYSACE_MPCE_LS"

LOC =

"W4";

##

 

NET "SYSACE_MPIRQ_LS"

LOC =

"AA2";

##

 

NET "SYSACE_MPOE_LS"

LOC =

"T6";

##

 

NET "SYSACE_MPWE_LS"

LOC =

"T5";

##

 

64

www.xilinx.com

SP605 Hardware User Guide

 

 

UG526 (v1.1.1) February 1, 2010

Page 63 Page 65
Image 64
Page 63 Page 65
Contents SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalRevision History Date Version RevisionTable of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideSP605 Evaluation Board Additional InformationFeatures SP605 Evaluation BoardBlock Diagram OverviewSP605 Features FeatureDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga MB DDR3 Component Memory Voltage RailsDetailed Description 2I/O Voltage Rail of Fpga BanksSchematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory ConnectionsU1 Fpga SPI x4 Flash 3J17 SPI Flash Programming HeaderSchematic Net Name Detailed Description 6SPI x4 Memory ConnectionsLinear BPI Flash Pin Number Pin NameFLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144IUSB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location IdentifiersSMA Connectors Differential Multi-Gigabit Transceivers GTP MGTsMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References SFP Module Connector Sfpclkqop14PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 USB-to-UART Bridge 17 USB-to-UART ConnectionsDVI Codec IIC Bus 11IIC Bus TopologyKb NV Memory IicsclsfpIicsdamain SDA Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 13Ethernet PHY Status LEDsFpga Init and Done LEDs 22 Fpga Init and Done LED ConnectionsUser I/O User LEDs23User LED Connections U1 Fpga Pin Controlled LEDUser Pushbutton Switches SW6User DIP Switch User SIP Header U1 Fpga PinUser SMA Gpio Usersmagpion UsersmagpiopSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and 12V Input Power Jack/SwitchOnboard Power Regulation Power ManagementUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET FmcpwrgoodflashrstbNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References
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