Xilinx Comprehensive Guide to GTP Transceivers and SMA Connectors in SP605

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Detailed Description

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50-ohm SMA connectors J38 (N) and J41 (P).

Table 1-9:SP605 Clock Source Connections

	Source	U1 FPGA Pin	Schematic Net Name	Pin	Pin Name
	Source	U1 FPGA Pin	Schematic Net Name	Number	Pin Name
				Number

	U6 200MHZ OSC	K22	SYSCLK_N	5	OUT_B

		K21	SYSCLK_P	4	OUT
		K21	SYSCLK_P	4	OUT

	X2 27MHZ OSC	AB13	USER_CLOCK	5	OUT

	USER_SMA_CLOCK	M19	USER_SMA_CLOCK_N	J38.1	–

	SMA Connectors	M20	USER_SMA_CLOCK_P	J41.1	–

8. Multi-Gigabit Transceivers (GTP MGTs)

The SP605 provides access to 4 MGTs.

•One (1) MGT is wired to the PCIe x1 Endpoint (P4) edge connector fingers

•One (1) MGT is wired to the FMC LPC connector (J2)

•One (1) MGT is wired to MGT SMA connectors (J36, J37)

•One (1) MGT is wired to the SFP Module connector (P4)

The SP605 includes a set of six SMA connectors for the GTP (MGT) RX/TX Port and GTP (MGT) Clock as described in Figure 1-10and Table 1-10.

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga Voltage Rails MB DDR3 Component MemoryDetailed Description 2I/O Voltage Rail of Fpga Banks5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector11 /100/1000 Tri-Speed Ethernet PHY 14PHY Configuration PinsBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsUser LEDs User I/O23User LED Connections U1 Fpga Pin Controlled LEDSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References