Xilinx SP605 manual USB-to-UART Bridge, USB-to-UART Connections

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Detailed Description

12. USB-to-UART Bridge

The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23). Table 1-16details the SP605 J23 pinout.

Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS UART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP605. Refer to the evaluation kit Getting Started Guide for driver installation instructions.

Table 1-16:USB Type B Pin Assignments and Signal Definitions

USB Connector

Signal Name

 

Description

 

Pin

 

 

 

 

 

 

 

 

 

 

 

1

VBUS

+5V from host system (not used)

 

 

 

 

 

 

2

USB_DATA_N

Bidirectional differential serial data (N-side)

 

 

 

 

 

3

USB_DATA_P

Bidirectional differential serial data (P-side)

 

 

 

 

 

4

GROUND

Signal ground

 

 

 

 

 

 

 

Table 1-17:USB-to-UART Connections

 

 

 

 

 

 

 

U1 FPGA Pin

UART Function

Schematic Net

U30 CP2103GM

UART Function

in FPGA

Name

Pin

in CP2103GM

 

 

 

 

 

 

F18

RTS, output

USB_1_CTS

22

CTS, input

 

 

 

 

 

F19

CTS, input

USB_1_RTS

23

RTS, output

 

 

 

 

 

B21

TX, data out

USB_1_RX

24

RXD, data in

 

 

 

 

 

H17

RX, data in

USB_1_TX

25

TXD, data out

 

 

 

 

 

Notes:

1.The schematic net names correspond with the CP2103GM pin names and functions, and the UART IP in the FPGA must be connected accordingly.

References

Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.

In addition, see some of the Xilinx UART IP specifications at:

•http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf

•http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Contents UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information SP605 Evaluation BoardSP605 Evaluation Board FeaturesOverview Block DiagramFeature SP605 FeaturesDetailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga Voltage Rails MB DDR3 Component MemoryDetailed Description 2I/O Voltage Rail of Fpga Banks5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin NameU1 Fpga 3J17 SPI Flash Programming Header SPI x4 FlashDetailed Description 6SPI x4 Memory Connections Schematic Net NamePin Number Pin Name Linear BPI FlashFLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash ConnectorU17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1USB Jtag Oscillator Differential Clock Generation8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orMulti-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialMGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector11 /100/1000 Tri-Speed Ethernet PHY 14PHY Configuration PinsBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga PinPHYRXD7 17 USB-to-UART Connections USB-to-UART BridgeDVI Codec 11IIC Bus Topology IIC BusIicsclsfp Kb NV MemoryIicsdamain SDA Status LEDs Signal Name Color Label Description13Ethernet PHY Status LEDs Ethernet PHY Status LEDs22 Fpga Init and Done LED Connections Fpga Init and Done LEDsUser LEDs User I/O23User LED Connections U1 Fpga Pin Controlled LEDSW6 User Pushbutton SwitchesUser DIP Switch U1 Fpga Pin User SIP HeaderUsersmagpion Usersmagpiop User SMA GpioPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighVita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC ConnectionsAC Adapter and 12V Input Power Jack/Switch Power ManagementPower Management Onboard Power RegulationUCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsFMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCFNET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References
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