Analog Devices ADSP-2192 specifications Preliminary Technical Data

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DSP Microcomputer

Preliminary Technical Data

ADSP-2192

ADSP-2192 DUAL-CORE DSP FEATURES

320MIP Dual ADSP-219x DSP in a 144-lead LQFP package with PCI, USB, Sub-ISA, and CardBus Interfaces

3.3V/5V PCI 2.2 Compliant 33MHz / 32-bit Interface with Bus Mastering over four DMA Channels with Scatter-Gather Support

Integrated USB 1.1 Compliant Interface

AC ‘97 serial interface supports external modem, handset, and audio codecs

Dual 160 MIPS ADSP-219x DSPs with 140K Words of Memory and 4K x 16-bit Shared Data Memory

DSP P0 Memory Includes: 64K x 16-bit Data Memory, 16K x 24-bit Program Memory, and Boot ROM

DSP P1 Memory Includes: 32K x 16-bit Data Memory, 16K x 24-bit Program Memory, and Boot ROM

ADSP-219X DSP CORE FEATURES

6.25ns Instruction Cycle Time (Internal), for up to 160 MIPS Sustained Performance

ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax

Single-cycle Instruction Execution

Dual Purpose Program Memory for Both Instruction and Data Storage

Fully Transparent Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle Unified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit Accumulators

 

 

 

 

 

 

 

 

 

P0

SHARED

P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

MEMORY

 

 

 

 

 

 

 

 

 

 

INTERRUPT CONTROLLER/

INTERRUPT CONTROLLER/

 

 

 

 

 

 

 

TIMER/FLAGS

 

MEMORY

 

 

TIMER/FLAGS

 

 

 

ADSP-219X

 

 

 

 

16K￿24 PM

16K￿24 PM

 

ADSP-219X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP CORE

 

 

 

 

 

 

 

 

4K￿16 DM

 

 

 

 

 

 

 

 

DSP CORE

 

 

 

 

 

CACHE

 

 

64K￿16 DM

32K￿16 DM

 

 

CACHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64 X 24-BIT

 

 

BOOT ROM

 

BOOT ROM

 

 

64 X 24-BIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDR

DATA

ADDR

DATA

ADDR

DATA

 

 

 

 

DAG1

DAG2

PROGRAM

 

 

 

 

 

 

 

 

PROGRAM

DAG2

DAG1

4X4X16

4X4X16

SEQUENCER

 

 

 

 

 

 

 

 

SEQUENCER

4X4X16

4X4X16

 

PM ADDRESS BUS

24

 

 

 

 

 

 

24

PM ADDRESS BUS

 

 

DM ADDRESS BUS

24

 

 

 

 

 

 

24

DM ADDRESS BUS

 

 

 

PM DATA BUS

24

 

 

 

 

 

 

24

PM DATA BUS

 

 

BUS

 

 

 

 

 

 

 

 

 

 

 

 

BUS

CONNECT

DM DATA BUS

16

 

 

 

 

 

 

16

DM DATA BUS

CONNECT

(PX)

 

 

 

 

 

 

 

 

 

 

 

 

(PX)

DATA

 

 

CORE

 

 

 

 

 

CORE

 

DATA

REGISTER

 

 

INTERFACE

 

 

 

 

 

INTERFACE

 

REGISTER

FILE

INPUT

 

 

 

 

 

 

 

 

 

 

INPUT

FILE

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTERS

 

 

 

 

 

 

 

 

 

 

REGISTERS

 

 

RESULT

 

 

ADDR

DATA

ADDR

DATA

ADDR

DATA

 

 

RESULT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTERS

 

 

P0 DMA

 

 

P1 DMA

 

 

REGISTERS

 

MULT

 

BARREL

ALU

 

 

ALU

BARREL

 

MULT

16 X 16-BIT

CONTROLLER

 

 

CONTROLLER

16 X 16-BIT

SHIFTER

 

 

SHIFTER

 

 

 

 

 

 

 

 

 

 

 

 

SHARED DSP

 

 

 

 

 

 

 

 

 

 

FIFOS

I/O MAPPED

FIFOS

 

 

 

 

 

 

 

 

REGISTERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P R O C E S S O R P 0

 

 

 

 

 

 

 

 

P R O C E S S O R P 1

 

GP I/O PINS

SERIAL PORT

HOST PORT

 

 

 

JTAG

(& OPTIONAL

 

PCI 2.2

AC'97

EMULATION

SERIAL

OR

PORT

COMPLIANT

EEPROM)

USB 1.1

 

 

 

Figure 1. ADSP-2192 Dual-Core DSP Block Diagram

 

 

 

 

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R

REV. PrA

 

 

 

 

 

A

 

 

 

 

 

N

 

L

 

 

 

 

 

I

 

 

 

 

 

M

 

A

 

 

 

I

 

C

 

 

 

L

 

 

 

 

 

E

 

H

I

 

 

This information applies to a product under development. Its characteristics

 

R

 

 

 

 

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106,NU.S.A.

 

 

 

 

C

T

 

and specifications are subject to change without notice. Analog Devices

Tel:781/329-4700

World Wide Web Site:Phttp://www.analog.comA

assumes no obligation regarding future manufacturing unless otherwise

Fax:781/326-8703

T

 

 

A

 

 

©AnalogEDevices,Inc., 2000

 

agreed to in writing.

 

 

 

 

D

 

 

 

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Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableADSP-2192 includes a 33MHz, 32 bit bus master PCI Industry standard AC’97 serial interface AC-LinkPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data ratesTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP memory accesses use BAR2 or BAR3 of each funcDSP, using the REG instruction BAR3 registers appear in on page 14 and TableRpci Dmah controller can be programmed to perform scat Mode the functions of the registers are mapped as followsADSP-2192 without processor intervention. In scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsRthroughHany function. As long as the Memory Space access Target accessesI to registers and DSP memory can goRegister or memory location within the ADSP-2192. Simi BistInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x4-0x5 DSP Memory Buffer Size 0x0-0x3 DSP Memory Buffer Base Addr0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR OffsetEP6 EP5EP7 EP8Release Number returned in the GET Device Descriptor command is contained in this register.Release Number is 0x0100, which corresponds to Device-specific attributes returned in the GETUSB EP5 NAK USB EP4 NAKUSB EP6 NAK USB EP7 NAKA21 INT = Active interrupt for the 8052 MCU ISE = Current interrupt is for a Setup tokenThisR registerHprovides information as the total size Fixed Endpoints Control EndpointADI 0x01 0x02 0x00REV. PrA A23 XXX USB McucodeBRequest 0xA0 USB RegioWValue L AddressWValue H A27 Packetsize, theNUSB core accepts it, as long as there is If for some reason the host sends more data than the maxSufficientCroom in theAFIFO Deassertion of PDW1 high causes a wake-up of the DSP Power themselves and the ADSP-2192 completely downAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master shouldFifo Interfaces reset the DSP under their control as needed SMSelIBit 3 Stereo / Mono Select AC’97 ModeEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 theseADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowManufacturer.I a parallel-resonant, fundamental frequency ForEthis configuration.TRmicroprocessorH -grade 24.576 MHz crystal should be used Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD1 AD0AD2 AD3130 CBE0 CBE1 CBE2 CBE3 CLKClkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA InterruptPAR IrdyPcignd PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Logic Reset Emulator Mode SelectEmulator Data Output Ctrlaux Ctrlvdd Ignd Acvaux Aiognd AvddIvdd Rvaux Rvdd TBD Specifications are subject to changeSupply Current Idle Supply Current Dynamic @ 160 Mips InternalInput Capacitance6 FIN=1 MHz VIN=2.5VAddress Setup to IOR / IOW Falling AEN Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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