Analog Devices ADSP-2192 specifications REV. PrA A47

Page 47

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For current information contact Analog Devices at (781) 461-3881

October 2000

ADSP-2192

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Table 38. 144-Lead LQFP

Table 38. 144-Lead LQFP

Table 38. 144-Lead LQFP

E

I

N

Pins By Signal

Pins By Signal

Pins By Signal

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H

A

P

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ADSP-2192

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SIGNAL

PIN #

SIGNAL

PIN #

SIGNAL

PIN #

144-LEAD LQFP

AD20

11

DEVSEL

24

IVDD

49

PINOUT

AD21

8

EMU

74

IVDD

58

AD22

7

17

IVDD

103

Table 38 lists the LQFP

FRAME

pinout by signal.

AD23

6

GND

111

IVDD

117

AD24

3

131

IVDD

125

Table 38. 144-Lead LQFP

GNT

Pins By Signal

AD25

2

IDSEL

5

IVDD

140

SIGNAL

PIN #

AD26

143

IGND

20

IVDD

62

102

ACRST

AD27

142

IGND

41

NC

115

ACVAUX

92

AD28

141

IGND

50

NC

114

ACVDD

93

AD29

138

IGND

59

NC

108

AD0

57

AD30

137

IGND

104

NC

105

AD1

56

AD31

136

IGND

120

NC

109

AD2

55

AGND

67

IGND

122

NC

107

AD3

54

AIOGND

91

IGND

126

NC

106

AD4

53

AQGND

68

IGND

139

NC

110

AD5

48

AVDD

65

INTAB

128

NC

127

AD6

47

ACVAUX

113

IO0

82

NC

70

AD7

46

ACVDD

112

IO1

83

NC

66

AD8

44

BITCLK

96

IO2

84

NC

94

AD9

43

BUS0

124

IO3

86

NC

69

AD10

42

BUS1

123

IO4

87

NC

95

AD11

37

45

IO5

88

PAR

31

CBE0

AD12

36

32

IO6

89

PCIGND

1

CBE1

AD13

35

16

IO7

90

PCIGND

10

CBE2

AD14

34

4

IOGND

76

PCIGND

21

CBE3

AD15

33

CLK

130

IOVDD

77

PCIGND

30

AD16

15

26

IOVDD

85

PCIGND

39

CLKRUN

AD17

14

CLKSEL

116

22

PCIGND

52

IRDY

AD18

13

CTRLAUX

61

IVDD

19

PCIGND

133

Y

R

AD19

12

A

CTRLVDD

63

IVDD

40

PCIVDD

N

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A

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E

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REV. PrA

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A47

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

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Image 47

Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableIfication. This interface supports the high data rates Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Pliant codecs to the ADSP-2192. The ACLink implementsBAR3 registers appear in on page 14 and Table DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP, using the REG instructionADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsBist Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Register or memory location within the ADSP-2192. SimiInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x8-0x9 DSP Memory Buffer WR Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x6-0x7 DSP Memory Buffer RD OffsetEP8 EP5EP6 EP7Device-specific attributes returned in the GET Descriptor command is contained in this register.Release Number returned in the GET Device Release Number is 0x0100, which corresponds toUSB EP7 NAK USB EP4 NAKUSB EP5 NAK USB EP6 NAKA21 Fixed Endpoints Control Endpoint ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU ThisR registerHprovides information as the total sizeREV. PrA A23 0x01 0x02 0x00ADI XXX USB McucodeAddress USB RegioBRequest 0xA0 WValue LWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is Pmeen output from the Combo Master should Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP An active lowIRST input to be derived from PCI RSTFifo Is shown as a no connect in on page 33 these SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode OnlyADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD3 AD0AD1 AD2131 128 PCI / ISA Interrupt CBE0 CBE1 CBE2 CBE3 CLK130 Clkrun Devsel Frame GNT Idsel IntabPcivdd IrdyPAR PcigndEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd TBD Specifications are subject to changeVIN=2.5V Supply Current Dynamic @ 160 Mips InternalSupply Current Idle Input Capacitance6 FIN=1 MHzIOR / IOW Strobe Width 100 AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling Write Data Setup to IOW RisingSub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.