Analog Devices ADSP-2192 0x0-0x3 DSP Memory Buffer Base Addr, 0x4-0x5 DSP Memory Buffer Size

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For current information contact Analog Devices at (781) 461-3881

 

 

 

 

October 2000

ADSP-2192

 

 

 

 

 

 

 

 

 

 

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16-bit PCIIDSP I/O Memory Map (BAR4)

 

 

 

 

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PCI Base Address Register (BAR 4) allows indirect access

 

 

 

 

 

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to the ADSP-2192 Control Registers and DSP Memory.

 

 

 

 

 

 

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The DSP Memory Indirect Access Registers accessible

 

 

 

 

from BAR4 are as follows:

 

 

 

 

 

 

Table 10. 16-bit PCI DSP I/O Space Indirect Access Registers Map (BAR 4 Mode)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset

 

 

Name

 

Reset

Comments

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x03-0x00

 

Control Register Address

0x0000

Address and direction control for registers accesses

 

 

 

 

 

 

 

 

 

 

 

 

0x07-0x04

 

Control Register Data

0x0000

Data for register accesses

 

 

 

 

 

 

 

 

 

 

 

 

0x0B-0x08

 

DSP Memory Address

0x000000

Address and Direction control for Indirect DSP

 

 

 

 

 

 

 

 

 

 

memory accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0F-0x0C

 

DSP Memory Data

0x000000

Data for DSP memory accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP P0 Memory Indirect Address Space occupies PCI BAR4 Space 0x000000 -> 0x01FFFF

DSP P1 Memory Indirect Address Space occupies PCI BAR4 Space 0x020000 -> 0x03FFFF

All Indirect DSP Memory Accesses are 24-bit or 16-bit Word Accesses.

Using the USB Interface

The ADSP-2192 USB design enables the ADSP-2192 to be configured and attached to a single device with multiple interfaces and various endpoint configurations, as follows:

1.Programmable descriptors and a class-specific com- mand interpreter are accessible through the USB 8052 registers. An 8052-compatible MCU is supported on-board, to enable soft downloading of different con- figurations, and support of standard or class-specific commands.

2.A total of 8 user-defined endpoints are provided. End- points can be configured as BULK, ISO, or INT, and can be grouped

USB DSP Register Definitions

For each endpoint, four registers are defined to provide a memory buffer in the DSP. These registers are defined for each endpoint shared by all defined interfaces, for a total of 4x8 = 32 registers. These registers are read/write by the DSP only.

Table 11. USB DSP Register Definitions

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REV. PrA

Address

Name

 

Comment

 

 

0x0-0x3

DSP Memory Buffer Base Addr

 

EP4

 

 

 

 

 

 

0x4-0x5

DSP Memory Buffer Size

 

EP4

 

 

 

 

 

 

0x6-0x7

DSP Memory Buffer RD Offset

 

EP4

 

 

 

 

 

 

0x8-0x9

DSP Memory Buffer WR Offset

 

EP4

 

 

 

 

 

 

0x10-0x13

DSP Memory Buffer Base Addr

 

EP5

 

 

 

 

 

 

0x14-0x15

DSP Memory Buffer Size

 

EP5

 

 

 

 

 

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0x16-0x17

DSP Memory Buffer RD Offset

 

EP5

 

 

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableADSP-2192 includes a 33MHz, 32 bit bus master PCI Industry standard AC’97 serial interface AC-LinkPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data ratesTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP memory accesses use BAR2 or BAR3 of each funcDSP, using the REG instruction BAR3 registers appear in on page 14 and TableADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsRthroughHany function. As long as the Memory Space access Target accessesI to registers and DSP memory can goRegister or memory location within the ADSP-2192. Simi BistInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x4-0x5 DSP Memory Buffer Size 0x0-0x3 DSP Memory Buffer Base Addr0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR OffsetEP6 EP5EP7 EP8Release Number returned in the GET Device Descriptor command is contained in this register.Release Number is 0x0100, which corresponds to Device-specific attributes returned in the GETUSB EP5 NAK USB EP4 NAKUSB EP6 NAK USB EP7 NAKA21 INT = Active interrupt for the 8052 MCU ISE = Current interrupt is for a Setup tokenThisR registerHprovides information as the total size Fixed Endpoints Control EndpointREV. PrA A23 0x01 0x02 0x00ADI XXX USB McucodeBRequest 0xA0 USB RegioWValue L AddressWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is Deassertion of PDW1 high causes a wake-up of the DSP Power themselves and the ADSP-2192 completely downAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master shouldFifo Interfaces reset the DSP under their control as needed SMSelIBit 3 Stereo / Mono Select AC’97 ModeEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 theseADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD1 AD0AD2 AD3130 CBE0 CBE1 CBE2 CBE3 CLKClkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA InterruptPAR IrdyPcignd PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd TBD Specifications are subject to changeSupply Current Idle Supply Current Dynamic @ 160 Mips InternalInput Capacitance6 FIN=1 MHz VIN=2.5VAddress Setup to IOR / IOW Falling AEN Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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