Analog Devices ADSP-2192 specifications SMSelIBit 3 Stereo / Mono Select AC’97 Mode

Page 31
REV. PrA
Power On Reset
USB Reset
PCI Reset
Power On Reset
System Reset Description
There are several sources of reset to the ADSP-2192.
RO (Bit 15): Receive Overflow - Sticky, Write-One-Clear. (0 = FIFO Overflow has not occurred or 1 = FIFO Overflow has occurred)
RFE (Bit 14): Receive FIFO Empty - Read Only. (0 = FIFO Not Empty or 1 = FIFO Empty)
RFF (Bit 13): Receive FIFO Full - Read Only. (0 = FIFO Not Full or 1 = FIFO Full)
DME (Bit 11): DMA Enable. (0 = DMA Disabled or 1 = DMA Enabled)
FIP (Bit 10–8): FIFO interrupt position. An interrupt is generated when FIP[2:0] + 1 words have been received in the FIFO. The interrupt is level-sensitive.
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For current information contact Analog Devices at (781) 461-3881

 

 

 

October 2000

ADSP-2192

 

 

 

 

 

 

 

 

 

 

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Note that PORST is not needed when using PCI or USB

 

 

SMSelI(Bit 3): Stereo / Mono Select - AC’97 Mode

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(and is shown as a no connect in Figure 8 on page 33); these

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Only.H(0 = Mono Stream or 1 = Stereo Stream)

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interfaces reset the DSP under their control as needed.

 

 

 

 

 

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•ESLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode

 

 

 

 

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Only.

 

 

 

DSP Software Reset

 

 

 

 

 

 

 

 

 

 

Table 26. AC’97 Slot Select Values

Slot

Mono

Stereo

 

 

 

 

 

 

0000–0010

Reserved

 

 

 

 

0011

Slot 3

Slots 3/4

 

 

 

0100

Slot 4

Slots 4/5

 

 

 

0101

Slot 5

Slots 5/6

 

 

 

0110

Slot 6

Slots 6/7

 

 

 

0111

Slot 7

Slots 7/8

 

 

 

1000

Slot 8

Slots 8/9

 

 

 

1001

Slot 9

Slots 9/10

 

 

 

1010

Slot 10

Slots 10/11

 

 

 

1011

Slot 11

Slots 11/12

 

 

 

1100

Slot 12

Not Allowed

 

 

 

1101–1111

Reserved

 

 

 

 

The DSP can generate a software reset using the RSTD bit in DSP Interrupt/Powerdown Registers). Generally, reset conditions are handled by forcing the DSPs to execute ROM- or RAM-based Reset Handler code. The Reset Han- dler that gets executed can be dictated by the Reset Source as defined by the CRST[1:0] bits in the Chip Mode/Status Register (CMSR).

The exact Reset Functionality is therefore defined by the ROM and RAM Reset Handler Code and as such is programmable.

Booting Modes

The ADSP-2192 has two mechanisms for automatically loading internal program memory after reset. The CRST pins, sampled during power on reset, implement these modes:

•Boot from PCI Host

•Boot from USB Host

Optionally, extra boot information can come from an SPI or Microwire serial EPROM during PCI or USB booting. The boot process flow appears in Figure 6 on page 32.

Power Management Description

The ADSP-2192 supports several states with distinct power management and functionality capabilities. These states encompass both hardware and software state.

The driver and DSP code take responsibility for detailed power management of the modem, so minimum power lev- els are achieved regardless of OS or BIOS. The driver and DSPs manage power by changing platform states as neces- sary in response to events.

Power Regulators

The ADSP-2192 is intended to operate in a variety of dif- ferent systems. These include PCI, CardBus, USB and imbedded (Sub-ISA) applications. The PCI and USB spec- ifications define power consumption limits that constrain the ADSP-2192 design.

2.5V Regulator Options

 

 

 

In 5V and 3.3V PCI applications the ADSP-2192 2.5V

 

 

 

 

IVDD supply will be generated by an on-chip regulator.

 

 

 

 

The internal 2.5V supply (IVDD) can be generated by the

Soft Reset (RST in CMSR Register)

on-chip regulator combined with an external power transis-

tor as shown in Figure 7 on page 32. To support the PCI

 

 

 

 

 

 

 

 

specification’s power down modes, the two transistors con-

 

 

 

trol the primary and auxiliary supply. If the reference

 

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The DSP has an internal power on reset circuit that resets

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voltage on RVDD (typically the same as PCIVDD) drops

 

the DSP when power is applied. The DSP also has a Power

 

 

 

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out, the VCTRLAUX will switch on the deviceMconnectedA

 

 

 

On Reset PORST signal that can initiate this master reset.

 

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Page 30 Page 32
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Page 30 Page 32
Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableIfication. This interface supports the high data rates Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Pliant codecs to the ADSP-2192. The ACLink implementsBAR3 registers appear in on page 14 and Table DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP, using the REG instructionRpci Dmah controller can be programmed to perform scat Mode the functions of the registers are mapped as followsADSP-2192 without processor intervention. In scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsBist Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Register or memory location within the ADSP-2192. SimiInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x8-0x9 DSP Memory Buffer WR Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x6-0x7 DSP Memory Buffer RD OffsetEP8 EP5EP6 EP7Device-specific attributes returned in the GET Descriptor command is contained in this register.Release Number returned in the GET Device Release Number is 0x0100, which corresponds toUSB EP7 NAK USB EP4 NAKUSB EP5 NAK USB EP6 NAKA21 Fixed Endpoints Control Endpoint ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU ThisR registerHprovides information as the total sizeADI 0x01 0x02 0x00REV. PrA A23 XXX USB McucodeAddress USB RegioBRequest 0xA0 WValue LWValue H A27 Packetsize, theNUSB core accepts it, as long as there is If for some reason the host sends more data than the maxSufficientCroom in theAFIFO Pmeen output from the Combo Master should Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP An active lowIRST input to be derived from PCI RSTFifo Is shown as a no connect in on page 33 these SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode OnlyADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowManufacturer.I a parallel-resonant, fundamental frequency ForEthis configuration.TRmicroprocessorH -grade 24.576 MHz crystal should be used Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD3 AD0AD1 AD2131 128 PCI / ISA Interrupt CBE0 CBE1 CBE2 CBE3 CLK130 Clkrun Devsel Frame GNT Idsel IntabPcivdd IrdyPAR PcigndEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Logic Reset Emulator Mode SelectEmulator Data Output Ctrlaux Ctrlvdd Ignd Acvaux Aiognd AvddIvdd Rvaux Rvdd TBD Specifications are subject to changeVIN=2.5V Supply Current Dynamic @ 160 Mips InternalSupply Current Idle Input Capacitance6 FIN=1 MHzIOR / IOW Strobe Width 100 AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling Write Data Setup to IOW RisingSub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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