Analog Devices ADSP-2192 specifications Loop stack interrupt enable

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					R					October 2000
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	ADSP-2192					For current information contact Analog Devices at (781) 461-3881
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		L						Table 3. Interrupt Control (ICNTL) register bits
	Table 2. DSP-to-DSP Semaphores Register Table
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P		C			A	DSP		Bit	Description
		E		T
	FlagT		DirectA-		Function	Core
	Bit		D			Flag	11		Loop stack interrupt enable
			ion
						In

12

Low power idle enable

3		Reserved
4		Reserved
5		Reserved
6		Reserved
7	Output	Register Bus Lock
8	Input	DSP-DSP Semaphore 0	0
9	Input	DSP-DSP Semaphore 1	1
10	Input	DSP-DSP Interrupt	2
11	Input	Reserved
12	Input	AC’97 Register - PDC Bus	4
		Access Status
13	Input	PDC Interface Busy Status	5
		(write from DSP pending)
14	Input	Reserved
15	Input	Register Bus Lock Status	7

13–15 Reserved

The IRPTL register is used to force and clear interrupts. On-chip stacks preserve the processor status and are auto- matically maintained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is

33-levels deep, the loop stack is eight-levels deep, and the status stack is sixteen-levels deep. To prevent stack overflow, the PC stack can generate a stack level interrupt if the PC stack falls below 3 locations full or rises above 28 locations full.

The following instructions globally enable or disable inter- rupt servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and computational registers exist. Switching between the primary and secondary registers lets programs quickly ser- vice interrupts, while preserving the DSP’s state.

DMA Controller

Interrupt routines can either be nested with higher priority			The ADSP-2192 has a DMA controller that supports auto-
			mated data transfers with minimal overhead for the DSP
interrupts taking precedence or processed sequentially.
			core. Cycle stealing DMA transfers can occur between the
Interrupts can be masked or unmasked with the IMASK
			ADSP-2192’s internal memory and any of its DMA capable
register. Individual interrupt requests are logically ANDed
			peripherals. Additionally, DMA transfers can also be
with the bits in IMASK; the highest priority unmasked
			accomplished between any of the DMA capable peripher-
interrupt is then selected. The emulation, power down, and
			als. DMA capable peripherals include the PCI and AC’97
reset interrupts are nonmaskable with the IMASK register,
			ports. Each individual DMA capable peripheral has a dedi-
but software can use the DIS INT instruction to mask the
			cated DMA channel. DMA sequences do not contend for
power down interrupt.
			bus access with the DSP core; instead, DMAs “steal” cycles
Table 3. Interrupt Control (ICNTL) register bits			to access memory.
			All DMA transfers use the Program Memory (PMA/PMD)
Bit		Description	buses shown in Figure 1 on page 1.
			External Interfaces
0–3		Reserved
			There are several different interfaces supported on the
4		Interrupt nesting enable
			ADSP-2192. These include both internal and external
5		Global interrupt enable	interfaces. The three separate PCI configuration spaces are
			programmable to set up the device in various Plug-and-Play
6		Reserved
			configurations.
			The ADSP-2192 provides the following types of external
7		MAC biased rounding enable							Y
			interfaces: PCI, USB, Sub-ISA, CardBus, AC’97, and
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8–9		Reserved	serial EEPROM. The following sections discuss those					A
			interfaces.				N		L
10		PC stack interrupt enable			I			A
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				L				IC
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	This information applies to a product under development. Its characteristics and specifications are subject to changePwith-				CREV. PrA A
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.			E				T
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