Analog Devices ADSP-2192 specifications Deassertion of PDW1 high causes a wake-up of the DSP

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For current information contact Analog Devices at (781) 461-3881

 

 

 

October 2000

 

ADSP-2192

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Deassertion of PDW1 high causes a wake-up of the DSP.

 

 

An active lowIRST input (to be derived from PCI RST and

 

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The PME_EN output from the Combo Master should

RpossibleHother sources) and an active-high IRQ interrupt

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Power Management is handled by the

reflect the current PCI function PME_EN bit and should

 

 

outputE are available.T

 

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be connected to the ADSP-2192 AD20 pin. The PMI_EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSP-D2192 inputs PDW1–0/PME_EN and the

 

 

 

 

 

ADSP-2192 output

PMERQ.

 

PDW1–0

should be the

bit should be set to enable interrupt and wake-up of the

 

 

inversion of the PCI power state in the function’s PMCSR

DSP upon any change of the PME_EN state. If PME_EN

 

 

register.

PDW1

 

is connected to AD21, and

PDW0

is con-

is turned off, the DSPs can wake up if necessary and then

 

 

nected to

AD20.

 

 

 

 

 

 

 

 

 

 

 

power themselves and the ADSP-2192 completely down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(clocks stopped).

 

 

 

Assertion of PDW1 low signals a power-down interrupt to

 

 

 

 

 

 

 

 

 

 

the DSP.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 24. Sub-ISA Indirect Access Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISAA[3:1]

 

 

 

 

 

 

Name

 

 

 

 

 

Reset

 

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0x0

 

 

 

 

 

 

 

 

 

 

Control Register Address

 

0x0000

 

Address and direction control for registers accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x1

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x2

 

 

 

 

 

 

 

 

 

 

Control Register Data

 

0x0000

 

Data for register accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x3

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x5-0x4

 

 

 

 

 

 

 

DSP Memory Address

 

0x000000

 

Address and direction control for DSP memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7-0x6

 

 

 

 

 

 

 

DSP Memory Data

 

0x000000

 

Data for DSP memory accesses.

 

 

 

 

 

 

 

 

 

 

 

 

PCI Interface to DSP Memory

 

 

 

AC’97 Codec Interface to DSP Memory

The PCI interface can directly access the DSP memory space using DMA transfers. The transactions can be either slave transfers, in which the host initiates the transaction, or master transfers, in which the ADSP-2192 initiates the PCI transaction. The registers that control PCI DMA transfers are accessible from both the DSP (on the Peripheral Device Control Bus) and the PCI Bus.

The PCI/Sub-ISA Bus uses the Peripheral Device Control Register Space which is distributed throughout the ADSP-2192 and connected through the Peripheral Device Control Bus. The PCI bus can access these registers directly.

USB Interface to DSP Memory

The USB interface can directly access the DSP memory space using DMA transfers to memory locations specified by the USB endpoints. The registers that control USB end- point DMA transfers are accessible from both the DSP (on the Peripheral Device Control Bus) and the USB Bus.

The Peripheral Device Control Register Space is distrib- uted throughout the ADSP-2192 and connected through the Peripheral Device Control Bus. The USB Bus can access these registers directly.

Transfers from AC’97 data to DSP memory are accom- plished using DMA transfer through the DSP FIFOs. Each DSP has four FIFOs available for data transfers to/from the AC’97 Codec Interface. The registers that control FIFO DMA transfers are only accessible from within the DSP and are defined as part of the core register space.

Data FIFO Architecture

Each DSP core within the ADSP-2192 contains four FIFOs which provide a data communication path to the rest of the chip. Two of the FIFOs are input FIFOs, receiving data into the DSP. The other two FIFOs are transmit FIFOs, sending data from the DSP to the codec, AC'97 interface, or the other DSP. Each FIFO is eight words deep and sixteen bits wide. Interrupts to the DSP can be generated when some words have been received in the input FIFOs, or when some words are empty in the Transmit FIFOs.

The interface to the FIFOs on the DSP is simply a register interface to the Peripheral Interface bus. TX0, RX0, TX1, and RX1 are the primary FIFO registers in the universal register map of the DSP. The FIFOs can be used to gener- ate interrupts to the DSP based upon FIFO transactions or can initiate DMA requests.

 

 

 

 

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

 

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Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableADSP-2192 includes a 33MHz, 32 bit bus master PCI Industry standard AC’97 serial interface AC-LinkPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data ratesTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP memory accesses use BAR2 or BAR3 of each funcDSP, using the REG instruction BAR3 registers appear in on page 14 and TableADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsRthroughHany function. As long as the Memory Space access Target accessesI to registers and DSP memory can goRegister or memory location within the ADSP-2192. Simi BistInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x4-0x5 DSP Memory Buffer Size 0x0-0x3 DSP Memory Buffer Base Addr0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR OffsetEP6 EP5EP7 EP8Release Number returned in the GET Device Descriptor command is contained in this register.Release Number is 0x0100, which corresponds to Device-specific attributes returned in the GETUSB EP5 NAK USB EP4 NAKUSB EP6 NAK USB EP7 NAKA21 INT = Active interrupt for the 8052 MCU ISE = Current interrupt is for a Setup tokenThisR registerHprovides information as the total size Fixed Endpoints Control EndpointREV. PrA A23 0x01 0x02 0x00ADI XXX USB McucodeBRequest 0xA0 USB RegioWValue L AddressWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is Deassertion of PDW1 high causes a wake-up of the DSP Power themselves and the ADSP-2192 completely downAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master shouldFifo Interfaces reset the DSP under their control as needed SMSelIBit 3 Stereo / Mono Select AC’97 ModeEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 theseADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD1 AD0AD2 AD3130 CBE0 CBE1 CBE2 CBE3 CLKClkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA InterruptPAR IrdyPcignd PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd TBD Specifications are subject to changeSupply Current Idle Supply Current Dynamic @ 160 Mips InternalInput Capacitance6 FIN=1 MHz VIN=2.5VAddress Setup to IOR / IOW Falling AEN Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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