Analog Devices specifications Register or memory location within the ADSP-2192. Simi, Bist, A11

					Y
					R
				A		For current information contact Analog Devices at (781) 461-3881
		October 2000						ADSP-2192
			N		L
			I
		M			A
		I		C
		L					register or memory location within the ADSP-2192. Simi-
		Target accessesI to registers and DSP memory can go
	E		N				larly, if IO Space access enable is set, then PCI I/O accesses
RthroughHany function. As long as the Memory Space access
P		C			A		can be performed via BAR4.
		enableE bit is Tset in that function, then PCI memory accesses
	T		A
		whose Daddresses match the locations programmed into a					Within the Power Management section of the configuration

function, BARs 1-3 will be able to read or write any visible	blocks, there are a few interactions. The part will stay in the
	highest power state between the three configurations.
Table 7. PCI Configuration Space 0, 1, and 2

Address

0x01-

0x00

0x03-

0x02

0x05-

0x04

0x07-

0x06

0x08

0x0B- 0x09

0x0C

0x0D

0x0E

0x0F

0x13-

0x10

0x17-

0x14

0x1B- 0x18

0x1F- 0x1C

0x23-

0x20

0x27-

0x24

0x2B- 0x28

REV. PrA

	Name	Reset	Comments
	Vendor ID	0x11D4	Writable from the DSP during initialization
	Config 0 Device ID	0x2192	Writable from the DSP during initialization
	Config 1 Device ID	0x219A	Writable from the DSP during initialization
	Config 2 Device ID	0x219E	Writable from the DSP during initialization
	Command Register	0x0	Bus Master, Memory Space Capable, I/O
			Space Capable
	Status Register	0x0	Bits enabled: Capabilities List, Fast B2B,
			Medium Decode
	Revision ID	0x0	Writable from the DSP during initialization
	Class Code	0x48000	Writable from the DSP during initialization
	Cache Line Size	0x0	Read-only
	Latency Timer	0x0
	Header Type	0x80	Multifunction bit set
	BIST	0x0	Unimplemented
	Base Address1	0x08	Register Access for all ADSP-2192 Registers,
			Prefetchable Memory
	Base Address2	0x08	24-bit DSP Memory Access
	Base Address3	0x08	16-bit DSP Memory Access
	Base Address4	0x01	I/O access for control registers and DSP
			memory
	Base Address5	0x0	Unimplemented
	Base Address6	0x0	Unimplemented
	Config 0 Cardbus CIS Pointer	0x1FF03	CIS RAM Pointer - Function 0 (Read Only).							Y
	Config 1 Cardbus CIS Pointer	0x1FE03							R
			CIS RAM Pointer - Function 1 (Read Only)A.
					N
				I						L
	Config 2 Cardbus CIS Pointer	0x1FD03		M					A
			CIS RAM Pointer - Function 2 (ReadI		Only).
			L					C
			E				I
					N
			R	H					A11
				C
This information applies to a product under development. Its characteristics and specifications are subjectPto change with-								T
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.
			T			A
				D