Analog Devices ADSP-2192 specifications Tion-level simulator a C/C++ compiler and a C/C++

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October 2000

 

 

 

 

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ADSP-2192

 

For current information contact Analog Devices at (781) 461-3881

 

 

 

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tion-level simulator; a C/C++ compiler; and a C/C++

Instruction Set Description

 

 

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run-time library that includes DSP and mathematical func-

TheRADSPH-2192 assembly language instruction set has an

 

 

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tions. Two key points for these tools are:

 

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algebraic syntax Tthat was designed for ease of coding and

 

 

 

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readability. The assembly language, which takes full advan-

• Compiled ADSP-219x C/C++ code efficiency—The

 

 

 

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tage of the processor’s unique architecture, offers the

compiler has been developed for efficient translation of

following benefits:

 

 

C/C++ code to ADSP-219x assembly. The DSP has

ADSP-219x assembly language syntax is a superset of

architectural features that improve the efficiency of

compiled C/C++ code.

 

 

and source code-compatible (except for two data regis-

 

 

ADSP-218x family code compatibility—The assembler

 

ters and DAG base address registers) with ADSP-218x

 

family syntax. You may need to restructure your 218x

has legacy features to ease the conversion of existing

 

programs, however, to accommodate the ADSP-2192’s

ADSP-218x applications to the ADSP-219x.

 

unified memory space and to conform to its interrupt

Debugging both C/C++ and assembly programs with the

 

 

 

 

 

 

 

vector map.

VisualDSP++ debugger, you can:

 

The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation.

View mixed C/C++ and assembly code (interleaved source and object information)

Insert break points

• Every instruction, except two, assembles into a single,

• Set conditional breakpoints on registers, memory, and

 

 

stacks

 

 

 

 

 

 

 

24-bit word that can execute in a single instruction

 

 

 

 

 

 

 

 

Trace instruction execution

 

 

 

 

 

 

 

cycle. The exceptions are two dual-word instructions,

 

 

 

 

 

 

 

one of which writes 16- or 24-bit immediate data to

Profile program execution

 

 

 

 

 

 

 

memory, and the other of which jumps/calls to other

• Fill and dump memory

 

 

 

 

 

 

 

pages in memory.

 

 

 

 

 

 

 

Source level debugging

 

 

 

 

 

 

Multi-function instructions allow parallel execution of

 

 

 

 

 

 

• Create custom debugger windows

 

 

 

 

 

 

 

an arithmetic, MAC, or shift instruction with up to two

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fetches or one write to processor memory space during

The VisualDSP++ IDE lets you define and manage DSP

 

 

a single instruction cycle.

software development. Its dialog boxes and property pages

 

• Supports a wider variety of conditional and uncondi-

enable you to configure and manage all of the ADSP-219x

 

 

tional jumps and calls and a larger set of conditions on

development tools, including the syntax highlighting in the

 

 

which to base execution of conditional instructions.

VisualDSP++ editor. This capability lets you:

 

 

 

 

 

Development Tools

• Control how the development tools process inputs and

 

 

generate outputs.

 

 

 

 

 

 

The ADSP-2192 is supported with a complete set of

 

 

 

 

 

 

 

• Maintain a one-to-one correspondence with the tool’s

 

VisualDSP++™ software and hardware development tools,

 

 

command line switches.

 

 

 

 

 

 

which include Analog Devices VisualDSP++ integrated

 

 

 

 

 

 

 

Analog Devices DSP emulators use the IEEE 1149.1 JTAG

 

development environment, evaluation kit, and emulators.

 

test access port of the ADSP-2192 processor to monitor

 

 

 

The JTAG emulator hardware used for other ADSP-219x

 

 

 

and control the target board processor during emulation.

 

DSPs, also fully emulates the ADSP-2192.

 

The emulator provides full-speed emulation, allowing

 

 

 

Both the ADSP-219x hardware development tools family

 

 

 

inspection and modification of memory, registers, and pro-

 

and the VisualDSP++ integrated project management and

 

cessor stacks. Non-intrusive in-circuit emulation is assured

 

debugging environment support the ADSP-2192. The

 

by the use of the processor’s JTAG interface; the emulator

 

VisualDSP++ project management environment enables

 

does not affect target system loading or timing.

 

 

 

 

 

you to develop and debug an application.

 

 

 

 

 

Note that the ADSP-2192 JTAG port does not support

 

 

 

The ADSP-219x software development environment,

 

 

 

boundary scan.

 

 

 

 

 

 

VisualDSP++, includes an easy-to-use assembler that is

 

 

 

 

 

 

In addition to the software and hardware development tools

 

based on an algebraic syntax; an archiver (librarian/library

 

available from Analog Devices, third parties provide a wide

 

builder); a linker; a loader; a cycle-accurate, instruc-

 

range of tools supporting the ADSP-219x processor family.

 

 

 

 

 

 

Hardware tools include ADSP-219x PC plug-in cards.

 

 

 

 

 

Third party software tools include DSP libraries, real-time

 

 

 

operating systems, and block diagram design tools.

 

 

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The emulator probe requires the ADSP-2192’s CLKIN,

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TMS, TCK, TRST, TDI, TDO, EMU, and GND signalsI

 

 

 

 

 

 

 

 

 

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be made accessible on the target system via a 14-Ipin con-

 

 

 

 

 

 

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Image 34
Contents Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16KREV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decrementedDSP-DSP Output DSP-DSP Semaphore DSP-DSP InterruptLoop stack interrupt enable ADSP-2192Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data ratesDSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and TableRpci Dmah controller can be programmed to perform scat Mode the functions of the registers are mapped as followsADSP-2192 without processor intervention. In scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel InterruptRegister or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access BistData Word. BAR3 Mode is typically used for Data Memory IntaPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused ReservedA15 7FFC 9FFC0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR OffsetEP7 EP5EP6 EP8Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GETUSB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAKA21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control EndpointADI 0x01 0x02 0x00REV. PrA A23 USB Mcucode XXXWValue L USB RegioBRequest 0xA0 AddressWValue H A27 Packetsize, theNUSB core accepts it, as long as there is If for some reason the host sends more data than the maxSufficientCroom in theAFIFO An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master shouldFifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 theseADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If aManufacturer.I a parallel-resonant, fundamental frequency ForEthis configuration.TRmicroprocessorH -grade 24.576 MHz crystal should be used Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical funcA35 AD2 AD0AD1 AD3Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA InterruptPcignd IrdyPAR PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Logic Reset Emulator Mode SelectEmulator Data Output Ctrlaux Ctrlvdd Ignd Acvaux Aiognd AvddIvdd Rvaux Rvdd Specifications are subject to change TBDInput Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5VWrite Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.