Analog Devices ADSP-2192 specifications A27

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For current information contact Analog Devices at (781) 461-3881

ADSP-2192

 

 

 

 

 

 

 

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specifies which endpoints are used (and

 

Table 22. Typical Configuration for FAX Modem

 

 

 

 

 

 

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theirHdefinitions). A typical configuration for ADSL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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EappearsTin Table 21.

 

 

 

Type

Comment

 

 

 

 

 

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A

 

 

 

 

 

Point

Packet

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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The user-defined driver downloads USB configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for interface 2, which is the FAX modem. Configura-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

BULK OUT

64

DSP CODE

 

 

 

 

 

 

 

tion specifies which endpoints are used and their

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

definitions. A typical configuration for FAX appears in

 

7

BULK IN

64

FAX RCV

 

 

 

 

 

 

 

Table 22.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

BULK OUT

64

FAX XMT

 

 

 

 

 

6.

The user-defined driver now writes the USB Config

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register, which causes the device to disconnect and

 

9

INT IN

16

STATUS

 

 

 

 

 

 

 

reconnect. The system enumerates all interfaces and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

loads the appropriate drivers.

 

 

The USB data FIFOs for these generic endpoints exist in

 

 

 

 

7.

ADSL driver downloads code to DSP for ADSL ser-

 

 

 

 

 

 

DSP memory space. For each endpoint, there exist the fol-

 

 

 

vice. DSP also initializes the USB Endpoint

 

 

 

 

 

lowing memory buffer registers:

 

 

 

 

 

 

 

 

 

 

 

 

 

Description Register, DSP Memory Buffer Base Addr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Base Address (18 bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register, DSP Memory Buffer Size Register, DSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Size (16 bits) - Offset from the Base Address

 

 

 

 

 

 

 

 

 

 

Memory Buffer RD Pointer Offset, and DSP Memory

 

 

 

 

 

 

 

 

 

 

 

Buffer WR Pointer Offset registers for each endpoint.

 

• Read Offset (16 bits) - Offset from the Base Address

 

 

 

 

 

 

Endpoints can only be used when these registers have

 

• Write Offset (16 bits) - Offset from the Base Address

 

 

 

 

 

 

been written. ADSL service is now available.

 

 

 

 

 

 

 

 

As part of initialization, the DSP code sets up these FIFOs

 

 

 

8.

FAX driver downloads code to DSP for FAX service.

 

 

 

 

 

before USB data transactions for these endpoints can begin.

 

 

 

DSP also initializes the USB Endpoint Description

 

 

 

 

 

DSP memory addresses cannot exceed 18 bits (0x000000 -

 

 

 

Register, DSP Memory Buffer Base Addr Register,

 

 

 

 

 

0x03FFFF). When setting up these USB FIFOs,

 

 

 

 

 

 

 

 

 

 

DSP Memory Buffer Size Register, DSP Memory

 

 

 

 

 

 

 

 

 

 

 

 

Base+Size/Read Off-set/ Write Offset cannot be greater

 

 

 

 

 

 

 

Buffer RD Pointer Offset, and DSP Memory Buffer

 

 

 

 

 

 

 

 

 

than 18 bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR Pointer Offset registers for each endpoint. End-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The DSP memory interface on the ADSP-2192 only allows

 

 

 

points can only be used when the above registers have

 

 

 

 

been written. FAX service is now available.

 

reads/writes of 16-bit words. It cannot handle byte transac-

 

 

ADSP-2192 USB Data Pipe Operations

 

 

tions. Therefore, a 64 byte maxpacketsize means 32 DSP

 

 

 

 

 

 

 

words. A single byte cannot be transferred to/from the DSP.

 

 

All data transactions involving the generic endpoints (4-11)

 

Endpoint 0 does not have this limitation. Since these FIFOs

 

 

stream data into and out of the DSP memory via a dedi-

 

exist in DSP memory, the DSP shares some pointer man-

 

 

 

 

cated USB hardware block. This hardware block manages

 

agement tasks with the USB core. For OUT transactions,

 

 

 

 

all USB transactions for these endpoints and serves as a

 

the write pointer is controlled by the USB core, while the

 

 

 

 

 

conduit for the data moving to and from the DSP memory

 

read pointer is governed by the DSP. The opposite is true

 

 

 

 

 

FIFOs. There is no MCU involvement in the management

 

for IN transactions.

 

 

 

 

 

 

 

 

 

 

 

 

 

of these data pipes.

 

 

 

Both the write and read pointers for each memory buffer

 

 

 

 

 

Table 21. Typical Configuration for ADSL Modem

 

would start off at zero. All USB buffers operate in a circular

 

 

 

fashion. Once a pointer reaches the end of the buffer, it will

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

need to be set back to zero.

 

 

 

 

 

 

 

 

 

 

 

 

 

End

 

Type

 

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Comment

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Point

 

 

Packet

 

OUT Transactions (Host -> Device)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When an OUT transaction arrives for a particular endpoint,

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

BULK OUT

64

DSP CODE

 

 

 

 

 

the USB core calculates the difference between the write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

BULK IN

64

ADSL RCV

 

and read pointers to determine the amount of room avail-

 

 

 

 

 

 

 

 

 

 

 

 

 

able in the FIFOs. If all of the OUT data arrives and the

 

 

 

 

 

5

 

 

BULK OUT

64

ADSL XMT

 

 

 

 

 

 

 

 

write pointer never catches up to the read pointer, that data

 

 

 

 

 

 

 

 

 

 

 

is Backed and the USB core updates the Memory Buffer

 

 

 

 

 

6

 

 

INT IN

16

STATUS

 

 

 

 

 

 

 

 

Write Offset register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If at any time during the transaction the two pointers col-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lide, the USB block responds with a NAK indicating that

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the host must re-send the same data packet; in that case,Rthe

 

 

 

 

 

 

 

 

 

 

 

write pointer remains unchanged.

 

 

 

 

 

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REV. PrA

 

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableIfication. This interface supports the high data rates Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Pliant codecs to the ADSP-2192. The ACLink implementsBAR3 registers appear in on page 14 and Table DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP, using the REG instructionMode the functions of the registers are mapped as follows Rpci Dmah controller can be programmed to perform scatADSP-2192 without processor intervention. In scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsBist Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Register or memory location within the ADSP-2192. SimiInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x8-0x9 DSP Memory Buffer WR Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x6-0x7 DSP Memory Buffer RD OffsetEP8 EP5EP6 EP7Device-specific attributes returned in the GET Descriptor command is contained in this register.Release Number returned in the GET Device Release Number is 0x0100, which corresponds toUSB EP7 NAK USB EP4 NAKUSB EP5 NAK USB EP6 NAKA21 Fixed Endpoints Control Endpoint ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU ThisR registerHprovides information as the total size0x01 0x02 0x00 ADIREV. PrA A23 XXX USB McucodeAddress USB RegioBRequest 0xA0 WValue LWValue H A27 If for some reason the host sends more data than the max Packetsize, theNUSB core accepts it, as long as there isSufficientCroom in theAFIFO Pmeen output from the Combo Master should Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP An active lowIRST input to be derived from PCI RSTFifo Is shown as a no connect in on page 33 these SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode OnlyADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowForEthis configuration.T Manufacturer.I a parallel-resonant, fundamental frequencyRmicroprocessorH -grade 24.576 MHz crystal should be used Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD3 AD0AD1 AD2131 128 PCI / ISA Interrupt CBE0 CBE1 CBE2 CBE3 CLK130 Clkrun Devsel Frame GNT Idsel IntabPcivdd IrdyPAR PcigndEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Mode Select Emulator Logic ResetEmulator Data Output Acvaux Aiognd Avdd Ctrlaux Ctrlvdd IgndIvdd Rvaux Rvdd TBD Specifications are subject to changeVIN=2.5V Supply Current Dynamic @ 160 Mips InternalSupply Current Idle Input Capacitance6 FIN=1 MHzIOR / IOW Strobe Width 100 AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling Write Data Setup to IOW RisingSub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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