Analog Devices ADSP-2192 specifications Dsp-Dsp, Output DSP-DSP Semaphore DSP-DSP Interrupt

Page 5

 

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

For current information contact Analog Devices at (781) 461-3881

ADSP-2192

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

October 2000

 

 

 

 

 

 

 

I

 

L

 

 

 

 

 

 

 

 

 

M

 

A

 

 

 

 

 

 

 

 

 

I

 

C

 

 

 

 

 

 

 

 

L

 

 

Table 2 on page 5 shows the interrupt vector and

 

 

mechanismsIto generate a 24-bit address for each bus. The

 

E

 

N

 

 

DSP-to-DSP semaphores at reset of each of the peripheral

RDSP hasHthree functions that support access to the full

P

 

 

C

 

 

A

 

interrupts. The peripheral interrupt’s position in the

 

 

memoryE

map.T

 

 

T

 

A

 

 

IMASK and IRPTL register and its vector address depend

 

 

 

D

 

 

 

 

 

• The DAGs generate 24-bit addresses for data fetches

on its priority level, as shown in Table 1 on page 5.

 

 

 

from the entire DSP memory address range. Because

 

 

 

 

 

 

 

 

 

 

 

DAG index (address) registers are 16 bits wide and

Table 1. Interrupt Vector Table

 

 

 

 

 

hold the lower 16-bits of the address, each of the DAGs

 

 

 

 

 

 

 

 

 

 

 

 

 

has its own 8-bit page register (DMPGx) to hold the

 

 

 

 

Vector

 

 

 

most significant eight address bits. Before a DAG gen-

 

Priorit

 

 

 

 

 

Bit

Interrupt

 

Address

 

 

 

erates an address, the program must set the DAG’s

y

 

 

 

 

 

 

 

Offset1

 

 

 

 

 

 

 

 

 

 

DMPGx register to the appropriate memory page.

 

 

 

 

 

 

 

• The Program Sequencer generates the addresses for

0

1

Reset (non-maskable)

0x00

 

 

 

instruction fetches. For relative addressing instruc-

 

 

 

 

 

 

 

 

1

2

Powerdown

 

0x04

 

 

 

tions, the program sequencer bases addresses for

 

 

 

 

 

 

(non-maskable)

 

 

 

 

 

relative jumps, calls, and loops on the 24-bit Program

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter (PC). In direct addressing instructions

2

3

Kernel interrupt (single

0x08

 

 

 

(two-word instructions), the instruction provides an

 

 

 

 

 

step)

 

 

 

 

 

immediate 24-bit address value. The PC allows linear

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

addressing of the full 24 bit address range.

3

4

Stack Status

 

0x0C

 

 

• For indirect jumps and calls that use a 16-bit DAG

 

 

 

 

 

 

 

4

5

Mailbox

 

0x10

 

 

 

address register for part of the branch address, the Pro-

 

 

 

 

 

 

 

 

 

 

 

 

gram Sequencer relies on an 8-bit Indirect Jump page

5

6

Timer

 

0x14

 

 

 

(IJPG) register to supply the most significant eight

 

 

 

 

 

 

 

 

6

7

Reserved

 

0x18

 

 

 

address bits. Before a cross page jump or call, the pro-

 

 

 

 

gram must set the program sequencer’s IJPG register to

 

 

 

 

 

 

 

 

7

8

PCI Bus Master

 

0x1C

 

 

 

the appropriate memory page.

 

 

 

 

 

 

 

 

 

 

 

Each ADSP-219x DSP core has an on-chip ROM that

8

9

DSP-DSP

 

0x20

 

 

holds boot routines. For more information, see “Booting

 

 

 

 

 

 

 

9

10

FIFO0 Transmit

 

0x24

 

 

Modes” on page 31.

 

 

 

 

 

 

 

 

 

 

 

 

Interrupts

 

 

 

10

11

FIFO0 Receive

 

0x28

 

 

 

 

 

 

 

 

 

 

 

 

The interrupt controller lets the DSP respond to thirteen

11

12

FIFO1 Transmit

 

0x2C

 

 

interrupts with minimum overhead. The controller imple-

 

 

 

 

 

 

 

12

13

FIFO1 Receive

 

0x30

 

 

ments an interrupt priority scheme as shown in Table 1 on

 

 

 

 

 

 

 

 

 

 

page 5. Applications can use the unassigned slots for soft-

 

 

 

 

 

 

 

13

14

Reserved

 

0x34

 

 

ware and peripheral interrupts. The DSP’s Interrupt

 

 

 

 

 

 

 

 

 

 

Control (ICNTL) register (shown in Table 3 on page 6)

14

15

Reserved

 

0x38

 

 

provides controls for global interrupt enable, stack interrupt

 

 

 

 

 

 

 

15

16

AC’97 Frame

 

0x3C

 

 

configuration, and interrupt nesting.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 The interrupt vector address values are represented as offsets from address 0x01 0000. This address corresponds to the start of Program Memory in DSP P0 and P1.

Table 2. DSP-to-DSP Semaphores Register Table

REV. PrA

 

 

 

 

 

 

 

 

DSP

 

 

 

Flag

Direct-

Function

 

 

 

 

Core

 

 

 

Bit

ion

 

 

 

 

Flag

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

Output

DSP-DSP Semaphore 0

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

 

 

 

1

Output

DSP-DSP Semaphore 1

 

 

 

 

R

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

L

 

2

Output

DSP-DSP Interrupt

 

 

I

 

 

 

M

 

A

 

 

 

 

I

 

 

C

 

 

 

 

 

L

 

 

 

 

 

 

 

 

E

 

 

 

 

I

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

R

 

H

 

 

 

 

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

 

A5

 

 

 

 

C

 

 

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

T

 

 

A

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

Page 4 Page 6
Image 5
Page 4 Page 6
Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableADSP-2192 includes a 33MHz, 32 bit bus master PCI Industry standard AC’97 serial interface AC-LinkPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data ratesTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP memory accesses use BAR2 or BAR3 of each funcDSP, using the REG instruction BAR3 registers appear in on page 14 and TableADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsRthroughHany function. As long as the Memory Space access Target accessesI to registers and DSP memory can goRegister or memory location within the ADSP-2192. Simi BistInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x4-0x5 DSP Memory Buffer Size 0x0-0x3 DSP Memory Buffer Base Addr0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR OffsetEP6 EP5EP7 EP8Release Number returned in the GET Device Descriptor command is contained in this register.Release Number is 0x0100, which corresponds to Device-specific attributes returned in the GETUSB EP5 NAK USB EP4 NAKUSB EP6 NAK USB EP7 NAKA21 INT = Active interrupt for the 8052 MCU ISE = Current interrupt is for a Setup tokenThisR registerHprovides information as the total size Fixed Endpoints Control EndpointREV. PrA A23 0x01 0x02 0x00ADI XXX USB McucodeBRequest 0xA0 USB RegioWValue L AddressWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is Deassertion of PDW1 high causes a wake-up of the DSP Power themselves and the ADSP-2192 completely downAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master shouldFifo Interfaces reset the DSP under their control as needed SMSelIBit 3 Stereo / Mono Select AC’97 ModeEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 theseADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD1 AD0AD2 AD3130 CBE0 CBE1 CBE2 CBE3 CLKClkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA InterruptPAR IrdyPcignd PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd TBD Specifications are subject to changeSupply Current Idle Supply Current Dynamic @ 160 Mips InternalInput Capacitance6 FIN=1 MHz VIN=2.5VAddress Setup to IOR / IOW Falling AEN Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
Top Page Image Contents